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PLD: Difference between revisions

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=== See Also ===
=== See Also ===
* [[PHD]]
* [[PLB]]
* [[PLB]]
* [[PLX]]
* [[PLX]]

Revision as of 06:49, 23 July 2023

Basic Info
Addressing Mode Opcode Length Speed
stack 2B 1 byte 5 cycles
Flags Clobbered
N V M X D I Z C
. . . . . .

PLD (PulL Direct page) is a 65c816 instruction that pulls the 16-bit value at the top of the stack into the direct page register.

See Also

External Links