TSET1 (SPC700): Difference between revisions

Revision as of 00:13, 24 July 2023


Basic Info
Addressing Mode	Opcode	Length	Speed
absolute	0E	3 byte	6 cycles


Flags Affected
N	V	P	B	H	I	Z	C
	.	.	.	.	.		.

TSET1 is an SPC700 instruction that tests and sets memory bits using the accumulator. For every set bit in the accumulator, the corresponding memory bit is also set.

External Links

Official Super Nintendo development manual on TSET1: Appendix C-9 of Book I

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-'''TSET1''' is an [[SPC700]] instruction that tests and sets bits with the [[accumulator]].
+'''TSET1''' is an [[SPC700]] instruction that tests and sets memory bits using the [[accumulator]].  For every set bit in the accumulator, the corresponding memory bit is also set.
 === See Also ===