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SEX (Super FX)

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Revision as of 19:33, 2 July 2024 by Xetheria (talk | contribs) (of the 3 types of implied 1 is the closest)
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Basic Info
Addressing Mode Opcode Length ROM Speed RAM Speed Cache Speed
Implied (type 1) 95 1 byte 3 cycles 3 cycles 1 cycle
Flags Affected
B ALT1 ALT2 O/V S CY Z
0 0 0 . .

SEX is a Super FX instruction that performs a sign extension of an 8-bit value. Bit 7 (the sign of the lower 8 bits) of the source register is copied into all the bits in the high byte of the destination register. The low byte of the source register is copied directly into the low byte of the destination register.

gsu sex.png

See Also

External Links