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CLD

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Revision as of 12:03, 15 July 2024 by Xetheria (talk | contribs) (→‎See Also: CLC, CLV)
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Basic Info
Addressing Mode Opcode Length Speed
Implied (type 2) D8 1 byte 2 cycles
Flags Affected
N V M X D I Z C
. . . . 0 . . .

CLD is a 65x instruction that clears the decimal mode flag, switching the processor back into binary mode so ADC and SBC will operate normally.

Syntax

CLD

See Also

External Links