TSET1 (SPC700)

Basic Info
Addressing Mode	Opcode	Length	Speed
Absolute	0E	3 bytes	6 cycles

Flags Affected
N	V	P	B	H	I	Z	C
	.	.	.	.	.		.

TSET1 is an SPC700 instruction that tests and sets memory bits using the accumulator. For every set bit in the accumulator, the corresponding memory bit is also set. In other words, a logical OR is performed.

Syntax

TSET1 !abs

Where abs is any address in the whole 64K bank.

See Also

• TCLR1
• SET1
• TSB

External Links

1. Official Super Nintendo development manual on TSET1: Table C-18 in Appendix C-9 of Book I
2. subparagraph 8.2.3.2 of page 3-8-8, lbid.

• anomie: https://github.com/yupferris/TasmShiz/blob/master/spc700.txt#L607