We've just updated MediaWiki and its underlying software. If anything doesn't look or work quite right, please mention it to us. --RanAS
SPC700/Waitstates
From SnesLab
This table shows how many waitstates the internal cycles of all the SPC700 opcodes have.
| 00..1F | 0 | 3 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 2 | 2 | 3 | 0 | 3 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 |
| 20..3F | 0 | 3 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 3 | 2 | 0 | 3 | 0 | 3 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 3 |
| 40..5F | 0 | 3 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 3 | 2 | 3 | 0 | 3 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
| 60..7F | 0 | 3 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 2 | 1 | 0 | 3 | 0 | 3 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |
| 80..9F | 0 | 3 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 2 | 3 | 0 | 3 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 10 | 3 |
| A0..BF | 1 | 3 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 3 | 0 | 3 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 |
| C0..DF | 1 | 3 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 7 | 2 | 3 | 0 | 3 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 4 | 1 |
| E0..FF | 0 | 3 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 3 | 0 | 3 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 3 | 0 |