S-DSP/Sample Generation Loop

The S-DSP's Sample Generation Loop takes 32 cycles to complete.

Note: most of this information was extracted from anomie's APU DSP doc with jwdonal.

Sample Generation Loop
Cycle Number	Action	Voice 0
0	Tick the SPC700 Stage 1 timers, always for T2 and every 4 samples for T0 and T1.	V0:S5
1		V0:S6
2		V0:S7
3		V0:S8
4		V0:S9
16	Tick the SPC700 Stage 1 timer for T2.
17		V0:S1
21		V0:S2
22	Apply ESA using the previously loaded value along with the previously calculated echo offset to calculate new echo pointer. Load left channel sample from the echo buffer. Load FFC0.	V0:S3a
23	Load right channel sample from the echo buffer. Load FFC1 and FFC2.
24	Load FFC3, FFC4, and FFC5.
25	Load FFC6 and FFC7.	V0:S3b
26	Load and apply MVOLL. Load and apply EVOLL. Output the left sample to the DAC. Load and apply EFB.
27	Load and apply MVOLR. Load and apply EVOLR. Output the right sample to the DAC. Load PMON
28	Load NON, EON, and DIR. Load FLG bit 5 (ECENx) for application to the left channel.
29	Update global counter. Write left channel sample to the echo buffer, if allowed by ECENx. Load EDL - if the current echo offset is 0, apply EDL. Load ESA for future use. Load FLG bit 5 (ECENx) again for application to the right channel. Clear internal KON bits for any channels keyed on in the previous 2 samples.
30	Write right channel sample to the echo buffer, if allowed by ECENx. Increment the echo offset, and set to 0 if it exceeds the buffer length. Load FLG bits 0-4 and update noise sample if necessary. Load KOFF and internal KON.	V0:S3c
31		V0:S4