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AND1 (SPC700): Difference between revisions
From SnesLab
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=== External Links === | === External Links === | ||
* Official Nintendo documentation on AND1: Table C-18 in [https://archive.org/details/SNESDevManual/book1/page/n234 Appendix C-9 of Book I] | * Official Nintendo documentation on AND1: Table C-18 in [https://archive.org/details/SNESDevManual/book1/page/n234 Appendix C-9 of Book I] | ||
* https://archive.org/details/SNESDevManual/book1/page/n186 | * [https://archive.org/details/SNESDevManual/book1/page/n186 page 3-8-8], lbid. | ||
[[Category:ASM]] | [[Category:ASM]] | ||
Revision as of 06:05, 18 December 2023
| Basic Info | |||||||
|---|---|---|---|---|---|---|---|
| Addressing Mode | Opcode | Length | Speed | ||||
| 13-bit Absolute | 4A | 3 bytes | 4 cycles | ||||
| 13-bit Absolute | 6A | 3 bytes | 4 cycles | ||||
| Flags Affected | |||||||
|---|---|---|---|---|---|---|---|
| N | V | P | B | H | I | Z | C |
| . | . | . | . | . | . | . | |
AND1 is an SPC700 instruction that performs a logical AND between a memory bit and the carry flag, then stores the conjunction in the carry flag. The low 13 bits of the operand specify an absolute address. The high 3 bits of the operand specify which bit at that absolute address.
See Also
External Links
- Official Nintendo documentation on AND1: Table C-18 in Appendix C-9 of Book I
- page 3-8-8, lbid.