We've just updated MediaWiki and its underlying software. If anything doesn't look or work quite right, please mention it to us. --RanAS
AND1 (SPC700): Difference between revisions
From SnesLab
(13/3 split) |
(→External Links: more correct subparagraph terminology) |
||
| (11 intermediate revisions by the same user not shown) | |||
| Line 7: | Line 7: | ||
|'''Speed''' | |'''Speed''' | ||
|+ | |+ | ||
| | |[[Absolute Boolean Bit]] | ||
|4A | |4A | ||
|3 bytes | |3 bytes | ||
|4 cycles | |4 cycles | ||
|+ | |+ | ||
| | |[[Absolute Boolean Bit]] | ||
|6A | |6A | ||
|3 bytes | |3 bytes | ||
| Line 19: | Line 19: | ||
{| class="wikitable" style="float:right;clear:right;width:30%" | {| class="wikitable" style="float:right;clear:right;width:30%" | ||
!colspan="8"|Flags | !colspan="8"|Flags Affected | ||
|+ | |+ | ||
|N | |[[Negative Flag|N]] | ||
|V | |[[Overflow Flag|V]] | ||
|P | |[[Direct Page Flag|P]] | ||
|B | |[[Break Flag|B]] | ||
|H | |[[Half-Carry Flag|H]] | ||
|I | |[[Interrupt Enable Flag|I]] | ||
|Z | |[[Zero Flag|Z]] | ||
|C | |[[Carry Flag|C]] | ||
|+ | |+ | ||
|. | |. | ||
| Line 41: | Line 41: | ||
'''AND1''' is an [[SPC700]] instruction that performs a logical AND between a memory bit and the [[carry flag]], then stores the conjunction in the carry flag. The low 13 bits of the operand specify an absolute address. The high 3 bits of the operand specify which bit at that absolute address. | '''AND1''' is an [[SPC700]] instruction that performs a logical AND between a memory bit and the [[carry flag]], then stores the conjunction in the carry flag. The low 13 bits of the operand specify an absolute address. The high 3 bits of the operand specify which bit at that absolute address. | ||
The [[bit reversal]] operator may be prefixed to the memory bit address, in which case opcode 6A is assembled. | |||
=== See Also === | === See Also === | ||
| Line 47: | Line 49: | ||
* [[EOR1]] | * [[EOR1]] | ||
* [[MOV1]] | * [[MOV1]] | ||
* [[NOT1]] | |||
=== External Links === | === External Links === | ||
* Official Nintendo documentation on AND1: [https://archive.org/details/SNESDevManual/book1/page/n234 Appendix C-9 of Book I] | * Official Nintendo documentation on AND1: Table C-18 in [https://archive.org/details/SNESDevManual/book1/page/n234 Appendix C-9 of Book I] | ||
* subparagraph 8.2.3.3 of [https://archive.org/details/SNESDevManual/book1/page/n186 page 3-8-8], lbid. | |||
[[Category:ASM]] | [[Category:ASM]] | ||
[[Category:SPC700]] | [[Category:SPC700]] | ||
[[Category:Bit Operation Commands]] | [[Category:Bit Operation Commands]] | ||
[[Category:Three-byte Instructions]] | |||
Latest revision as of 13:23, 29 December 2023
| Basic Info | |||||||
|---|---|---|---|---|---|---|---|
| Addressing Mode | Opcode | Length | Speed | ||||
| Absolute Boolean Bit | 4A | 3 bytes | 4 cycles | ||||
| Absolute Boolean Bit | 6A | 3 bytes | 4 cycles | ||||
| Flags Affected | |||||||
|---|---|---|---|---|---|---|---|
| N | V | P | B | H | I | Z | C |
| . | . | . | . | . | . | . | |
AND1 is an SPC700 instruction that performs a logical AND between a memory bit and the carry flag, then stores the conjunction in the carry flag. The low 13 bits of the operand specify an absolute address. The high 3 bits of the operand specify which bit at that absolute address.
The bit reversal operator may be prefixed to the memory bit address, in which case opcode 6A is assembled.
See Also
External Links
- Official Nintendo documentation on AND1: Table C-18 in Appendix C-9 of Book I
- subparagraph 8.2.3.3 of page 3-8-8, lbid.