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AND (SPC700): Difference between revisions

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=== External Links ===
=== External Links ===
* Official Super Nintendo development manual on AND: [https://archive.org/details/SNESDevManual/book1/page/n231 Appendix C-6 of Book I]
* Official Super Nintendo development manual on AND: Table C-8 in [https://archive.org/details/SNESDevManual/book1/page/n231 Appendix C-6 of Book I]


[[Category:ASM]]
[[Category:ASM]]
[[Category:SPC700]]
[[Category:SPC700]]
[[Category:8-bit Logic Operation Commands]]
[[Category:8-bit Logic Operation Commands]]

Revision as of 09:20, 20 November 2023

Basic Info
Addressing Mode Opcode Length Speed
Immediate 28 2 bytes 2 cycles
Implied Indirect (type 1) 26 1 byte 3 cycles
Direct Page 24 2 bytes 3 cycles
Direct Page Indexed by X 34 2 bytes 4 cycles
Absolute 25 3 bytes 4 cycles
Absolute Indexed by X 35 3 bytes 5 cycles
Absolute Indexed by Y 36 3 bytes 5 cycles
Direct Page Indexed by X 27 2 bytes 6 cycles
Direct Page Indirect Indexed by Y 37 2 bytes 6 cycles
Implied Indirect (type 1) 39 1 bytes 5 cycles
Direct Page 29 3 bytes 6 cycles
Direct Page Immediate 38 3 bytes 5 cycles
Flags Affected
N V P B H I Z C
. . . . . .

AND is an SPC700 instruction that performs a logical conjunction.

The operands are stored in the instruction stream in the opposite order they appear in the assembler source. In the assembler source, the operand on the right is the source and the operand on the left is the destination.

See Also

External Links