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DEC (SPC700): Difference between revisions

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(dp admodes)
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|5 cycles
|5 cycles
|+
|+
|
|[[Absolute Addressing | Absolute]]
|8C
|8C
|3 bytes
|3 bytes
|5 cycles
|5 cycles
|+
|+
|
|[[Implied]] (type 1)
|1D
|1D
|1 byte
|1 byte
|2 cycles
|2 cycles
|+
|+
|
|[[Implied]] (type 1)
|DC
|DC
|1 byte
|1 byte
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{| class="wikitable" style="float:right;clear:right;width:30%"
{| class="wikitable" style="float:right;clear:right;width:30%"
!colspan="8"|Flags Clobbered
!colspan="8"|Flags Affected
|+
|+
|N
|[[Negative Flag|N]]
|V
|[[Overflow Flag|V]]
|P
|[[Direct Page Flag|P]]
|B
|[[Break Flag|B]]
|H
|[[Half-Carry Flag|H]]
|I
|[[Interrupt Enable Flag|I]]
|Z
|[[Zero Flag|Z]]
|C
|[[Carry Flag|C]]
|+
|+
|
|

Latest revision as of 05:01, 27 November 2023

Basic Info
Addressing Mode Opcode Length Speed
Accumulator 9C 1 byte 2 cycles
Direct Page 8B 2 byte 4 cycles
Direct Page Indexed by X 9B 2 byte 5 cycles
Absolute 8C 3 bytes 5 cycles
Implied (type 1) 1D 1 byte 2 cycles
Implied (type 1) DC 1 byte 2 cycles
Flags Affected
N V P B H I Z C
. . . . . .

DEC is an SPC700 instruction that decrements its operand.

See Also

External Links

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