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EOR (SPC700): Difference between revisions

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'''EOR''' is an [[SPC700]] instruction that performs an exclusive or.
{| class="wikitable" style="float:right;clear:right;width:40%"
{| class="wikitable" style="float:right;clear:right;width:40%"
!colspan="8"|Basic Info
!colspan="8"|Basic Info
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|'''Speed'''
|'''Speed'''
|+
|+
|
|[[Immediate]]
|48
|48
|2 bytes
|2 bytes
|2 cycles
|2 cycles
|+
|+
|
|[[Implied Indirect]] (type 2)
|46
|46
|1 byte
|1 byte
|3 cycles
|3 cycles
|+
|+
|
|[[Direct Page Addressing | Direct Page]]
|44
|44
|2 bytes
|2 bytes
|3 cycles
|3 cycles
|+
|+
|
|[[Direct Page Indexed by X]]
|54
|54
|2 bytes
|2 bytes
|4 cycles
|4 cycles
|+
|+
|
|[[Absolute Addressing | Absolute]]
|45
|45
|3 bytes
|3 bytes
|4 cycles
|4 cycles
|+
|+
|
|[[Absolute Indexed by X]]
|55
|55
|3 bytes
|3 bytes
|5 cycles
|5 cycles
|+
|+
|
|[[Absolute Indexed by Y]]
|56
|56
|3 bytes
|3 bytes
|5 cycles
|5 cycles
|+
|+
|
|[[Direct Page Indexed Indirect by X]]
|47
|47
|2 bytes
|2 bytes
|6 cycles
|6 cycles
|+
|+
|
|[[Direct Page Indirect Indexed by Y]]
|57
|57
|2 bytes
|2 bytes
|6 cycles
|6 cycles
|+
|+
|
|[[Implied Indirect]] (type 1)
|59
|59
|1 bytes
|1 bytes
|5 cycles
|5 cycles
|+
|+
|
|[[Direct Page]]
|49
|49
|3 bytes
|3 bytes
|6 cycles
|6 cycles
|+
|+
|
|[[Direct Page Immediate]]
|58
|58
|3 bytes
|3 bytes
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{| class="wikitable" style="float:right;clear:right;width:30%"
{| class="wikitable" style="float:right;clear:right;width:30%"
!colspan="8"|Flags Clobbered
!colspan="8"|Flags Affected
|+
|+
|N
|[[Negative Flag|N]]
|V
|[[Overflow Flag|V]]
|P
|[[Direct Page Flag|P]]
|B
|[[Break Flag|B]]
|H
|[[Half-Carry Flag|H]]
|I
|[[Interrupt Enable Flag|I]]
|Z
|[[Zero Flag|Z]]
|C
|[[Carry Flag|C]]
|+
|+
|
|
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'''EOR''' is an [[SPC700]] instruction that performs an exclusive or.
The operands are stored in the instruction stream in the opposite order they appear in the assembler source. In the assembler source, the operand on the right is the source and the operand on the left is the destination.


=== See Also ===
=== See Also ===
* [[EOR1]]
* [[EOR1]]
* [[AND (SPC700)]]
* [[OR (SPC700)]]
* [[EOR]]


=== External Links ===
=== External Links ===

Latest revision as of 04:57, 27 November 2023

Basic Info
Addressing Mode Opcode Length Speed
Immediate 48 2 bytes 2 cycles
Implied Indirect (type 2) 46 1 byte 3 cycles
Direct Page 44 2 bytes 3 cycles
Direct Page Indexed by X 54 2 bytes 4 cycles
Absolute 45 3 bytes 4 cycles
Absolute Indexed by X 55 3 bytes 5 cycles
Absolute Indexed by Y 56 3 bytes 5 cycles
Direct Page Indexed Indirect by X 47 2 bytes 6 cycles
Direct Page Indirect Indexed by Y 57 2 bytes 6 cycles
Implied Indirect (type 1) 59 1 bytes 5 cycles
Direct Page 49 3 bytes 6 cycles
Direct Page Immediate 58 3 bytes 5 cycles
Flags Affected
N V P B H I Z C
. . . . . .

EOR is an SPC700 instruction that performs an exclusive or.

The operands are stored in the instruction stream in the opposite order they appear in the assembler source. In the assembler source, the operand on the right is the source and the operand on the left is the destination.

See Also

External Links

Retrieved from "https://sneslab.net/mw/index.php?title=EOR_(SPC700)&oldid=11102"