EOR (SPC700): Difference between revisions

Latest revision as of 04:57, 27 November 2023


Basic Info
Addressing Mode	Opcode	Length	Speed
Immediate	48	2 bytes	2 cycles
Implied Indirect (type 2)	46	1 byte	3 cycles
Direct Page	44	2 bytes	3 cycles
Direct Page Indexed by X	54	2 bytes	4 cycles
Absolute	45	3 bytes	4 cycles
Absolute Indexed by X	55	3 bytes	5 cycles
Absolute Indexed by Y	56	3 bytes	5 cycles
Direct Page Indexed Indirect by X	47	2 bytes	6 cycles
Direct Page Indirect Indexed by Y	57	2 bytes	6 cycles
Implied Indirect (type 1)	59	1 bytes	5 cycles
Direct Page	49	3 bytes	6 cycles
Direct Page Immediate	58	3 bytes	5 cycles


Flags Affected
N	V	P	B	H	I	Z	C
	.	.	.	.	.		.

EOR is an SPC700 instruction that performs an exclusive or.

The operands are stored in the instruction stream in the opposite order they appear in the assembler source. In the assembler source, the operand on the right is the source and the operand on the left is the destination.

External Links

Official Super Nintendo development manual on EOR: Appendix C-6 of Book I

@@ Line 69: / Line 69: @@
 {| class="wikitable" style="float:right;clear:right;width:30%"
-!colspan="8"|Flags Clobbered
+!colspan="8"|Flags Affected
 |+
-|N
+|[[Negative Flag|N]]
-|V
+|[[Overflow Flag|V]]
-|P
+|[[Direct Page Flag|P]]
-|B
+|[[Break Flag|B]]
-|H
+|[[Half-Carry Flag|H]]
-|I
+|[[Interrupt Enable Flag|I]]
-|Z
+|[[Zero Flag|Z]]
-|C
+|[[Carry Flag|C]]
 |+
 |
@@ Line 91: / Line 91: @@
 '''EOR''' is an [[SPC700]] instruction that performs an exclusive or.
+The operands are stored in the instruction stream in the opposite order they appear in the assembler source. In the assembler source, the operand on the right is the source and the operand on the left is the destination.
 === See Also ===