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LSR: Difference between revisions
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|'''Speed''' | |'''Speed''' | ||
|+ | |+ | ||
| | |[[Accumulator Addressing|Accumulator]] | ||
|4A | |4A | ||
|1 byte | |1 byte | ||
|2 cycles | |2 cycles | ||
|+ | |+ | ||
| | |[[Absolute]] | ||
|4E | |4E | ||
|3 bytes | |3 bytes | ||
|6 cycles | |6 cycles* | ||
|+ | |+ | ||
| | |[[Direct Page Addressing|Direct Page]] | ||
|46 | |46 | ||
|2 bytes | |2 bytes | ||
|5 cycles | |5 cycles* | ||
|+ | |+ | ||
|absolute indexed X | |absolute indexed X | ||
|5E | |5E | ||
|3 bytes | |3 bytes | ||
|7 cycles | |7 cycles* | ||
|+ | |+ | ||
|direct page indexed X | |direct page indexed X | ||
|56 | |56 | ||
|2 bytes | |2 bytes | ||
|6 cycles | |6 cycles* | ||
|} | |} | ||
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!colspan="9"|Flags Affected | !colspan="9"|Flags Affected | ||
|+ | |+ | ||
|N | |[[N Flag|N]] | ||
|V | |[[V Flag|V]] | ||
|M | |[[M Flag|M]] | ||
|X | |[[X Flag|X]] | ||
|D | |[[D Flag|D]] | ||
|I | |[[I Flag|I]] | ||
|Z | |[[Z Flag|Z]] | ||
|C | |[[C Flag|C]] | ||
|+ | |+ | ||
|0 | |0 | ||
Line 56: | Line 56: | ||
'''LSR''' (Logical Shift Right) is a 65x instruction that shifts a value one bit to the right (division by two). The most significant bit becomes a zero. The least significant bit is shifted into the [[carry flag]]. | '''LSR''' (Logical Shift Right) is a 65x instruction that shifts a value one bit to the right (division by two). The most significant bit becomes a zero. The least significant bit is shifted into the [[carry flag]]. | ||
===== Cycle Penalties ===== | |||
* Except in [[accumulator addressing]], LSR takes an extra two cycles when the accumulator is 16 bits wide | |||
* In [[direct page addressing]] modes, LSR takes another extra cycle if the low byte of the [[direct page register]] is nonzero. | |||
=== See Also === | === See Also === | ||
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=== External Links === | === External Links === | ||
* [[Eyes & Lichty]] page on LSR: https://archive.org/details/0893037893ProgrammingThe65816/page/n491 | * [[Eyes & Lichty]] page 465, on LSR: https://archive.org/details/0893037893ProgrammingThe65816/page/n491 | ||
* [[Labiak]] page on LSR: https://archive.org/details/Programming_the_65816/page/n162 | * [[Labiak]] page 152 on LSR: https://archive.org/details/Programming_the_65816/page/n162 | ||
* [[MCS6500 Manual]] page on LSR: https://archive.org/details/mos_microcomputers_programming_manual/page/n169 | * [[MCS6500 Manual]] page 148 on LSR: https://archive.org/details/mos_microcomputers_programming_manual/page/n169 | ||
* [[Carr]] page on LSR: https://archive.org/details/6502UsersManual/page/n278 | * [[Carr]] page 265 on LSR: https://archive.org/details/6502UsersManual/page/n278 | ||
* [[Leventhal]] page on LSR: https://archive.org/details/6502-assembly-language-programming/page/n125 | * [[Leventhal]] page 3-76 on LSR: https://archive.org/details/6502-assembly-language-programming/page/n125 | ||
* snes9x implementation of LSR: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L862 | * snes9x implementation of LSR: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L862 | ||
* undisbeliever on LSR: https://undisbeliever.net/snesdev/65816-opcodes.html#lsr-logical-shift-right | * undisbeliever on LSR: https://undisbeliever.net/snesdev/65816-opcodes.html#lsr-logical-shift-right |
Latest revision as of 04:34, 6 December 2023
Basic Info | |||||||
---|---|---|---|---|---|---|---|
Addressing Mode | Opcode | Length | Speed | ||||
Accumulator | 4A | 1 byte | 2 cycles | ||||
Absolute | 4E | 3 bytes | 6 cycles* | ||||
Direct Page | 46 | 2 bytes | 5 cycles* | ||||
absolute indexed X | 5E | 3 bytes | 7 cycles* | ||||
direct page indexed X | 56 | 2 bytes | 6 cycles* |
Flags Affected | ||||||||
---|---|---|---|---|---|---|---|---|
N | V | M | X | D | I | Z | C | |
0 | . | . | . | . | . |
LSR (Logical Shift Right) is a 65x instruction that shifts a value one bit to the right (division by two). The most significant bit becomes a zero. The least significant bit is shifted into the carry flag.
Cycle Penalties
- Except in accumulator addressing, LSR takes an extra two cycles when the accumulator is 16 bits wide
- In direct page addressing modes, LSR takes another extra cycle if the low byte of the direct page register is nonzero.
See Also
External Links
- Eyes & Lichty page 465, on LSR: https://archive.org/details/0893037893ProgrammingThe65816/page/n491
- Labiak page 152 on LSR: https://archive.org/details/Programming_the_65816/page/n162
- MCS6500 Manual page 148 on LSR: https://archive.org/details/mos_microcomputers_programming_manual/page/n169
- Carr page 265 on LSR: https://archive.org/details/6502UsersManual/page/n278
- Leventhal page 3-76 on LSR: https://archive.org/details/6502-assembly-language-programming/page/n125
- snes9x implementation of LSR: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L862
- undisbeliever on LSR: https://undisbeliever.net/snesdev/65816-opcodes.html#lsr-logical-shift-right