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Left Right Clock: Difference between revisions
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[[File:lrck schematic.png|thumb|The left right clock is in region C4 of the [[jwdonal schematic]]]] | |||
The '''Left Right Clock''' controls stereo processing. The rising and falling edges of this clock tell when processing for one stereo channel begins and the other stops. It is denoted '''LRCK''', and connected to pin 13 of the 16-bit [[Stereo DAC]] and pin 43 of the [[Sony S-DSP]] sound chip. | |||
In 2023, it was observed that this clock starts out slow and slowly speeds up as it gets warmer. <sup>[2]</sup> | |||
=== References === | |||
# https://forums.nesdev.org/viewtopic.php?p=285045#p285045 | |||
# https://forums.nesdev.org/viewtopic.php?t=24610 | |||
[[Category:SNES Hardware]] | |||
[[Category:Audio]] | |||
[[Category:Traces]] | |||
[[Category:Timing]] | |||
Latest revision as of 03:06, 17 July 2023
The left right clock is in region C4 of the jwdonal schematic
The Left Right Clock controls stereo processing. The rising and falling edges of this clock tell when processing for one stereo channel begins and the other stops. It is denoted LRCK, and connected to pin 13 of the 16-bit Stereo DAC and pin 43 of the Sony S-DSP sound chip.
In 2023, it was observed that this clock starts out slow and slowly speeds up as it gets warmer. [2]