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=== [https://archive.org/details/SNESDevManual/book2/page/n406 Index for Book I]===
=== [https://archive.org/details/SNESDevManual/book2/page/n406 Index for Book I]===
* Absolute Addressing 1-17-4
* Absolute Multiplication 1-15-1
* Addition/Subtraction Screen 1-7-1
* ADSR Mode 2-7-3
* Audio Processing Unit 1-22-1
* BG Mode 1-3-1, 1-27-3
* Bit Rate Reduction 2-2-1
* Brightness 1-27-1
* BRR 2-2-1, 2-7-9
* BRR Filter 2-2-1, 2-2-2
* BRR Filter Number 2-2-1
* BRR Format 2-2- 1
* BRR Range 2-2-1, 2-2-2
* CG-RAM 1-8-1, 1-27-11
* Channels 1-17-1
* Clock Speed 1-21-1
* Color Constant 1-7-2
* Color Constant Addition/Subtraction 1-7-5, 1-9-1
* Color Generator RAM 1-22-2
* Colors 1-2-1
* Controller 1-13-1, 1-14-1
* CPU Clock 1-21-1
* Data Bank Register 3-3-2, 3-4-5, 3-4-8
* Data Transfer 1-17-1
* Direct Page Flag 2-8-7
* Direct Register 3-4-8
* Direct Select 1-27-16
* Division 1-15-1
* DMA 1-13-1, 1-17-1
* DMA, General Purpose 1-13-1, 1-17-1
* Echo Delay 2-7-9
* Echo Enable 2-7-8
* Echo Feed-Back 2-7-9
* Echo Filter Coefficients 2-7-1
* Echo Start Address 2-7-9
* Emulation Mode 3-1-1, 3-2-1
* Expanded Connector 1-13-1
* ExtBG Mode 1-5-1, 1-27-19
* External Latch Flag 1-27-22, 4-1-3
* External Synchronization 1-27-19
* Fixed Color Addition 1-6-1 G
* Gain Mode 2-7-3
* H-Blank 1-17-4
* H-DMA 1-6-1, 1-12-1, 1-17-1
* Horizontal Blanking 1-1-2
* Indirect Addressing 1-17-4
* Interface 1-14-1
* Interlace 1-1-1, 1-1-2, 1-18-1
* Interrupt 1-16-1
* IPL ROM 2-1-1
* Joy Controller Enable 1-28-1 M
* Main Screen 1-7-1, 1-7-5
* Mode 20 1-21-3
* Mode 21 1-21-4
* Mosaic 1-4-1, 1-27-3
* Multiplication 1-27-20
* Native Mode 3-2-1
* NMI 1-13-1
* OAM Priority Rotation 1-27-2
* Object Attribute Memory 1-22-2, 1-27-2
* Object Size 1-27-1
* Pallets 1-2-1
* Priority 1-2-1
* Priority Order 1-20-2
* Processor Status Register 3-9-2
* Programmable I/O Port 1-14-1, 1-28-1
* Program Bank Register 3-3-3, 3-4-7
* Program Counter 3-3-3
* Program Status Word 2-8-6
* Resolution 1-3-1, 1-18-1 S
* Screen Addition/Subtraction 1-6-1, 1-7-5, 1-9-1
* Screen Repetition 1-27-4
* Scroll 1-12-1
* Scroll, Vertical Partial 1-12-1
* Sony SPC700 2-8-1
* Stack Pointer 3-3-3
* Sub Screen 1-7-1, 1-7-5
* Synchronization 1-16-1
* Timer 1-16-1
* Timer Enable 1-28-1
* Transparency 1-7-2
* Two’s Complement 1-10-1
* Vertical Blanking 1-1-2 W
* Window 1-6-1, 1-12-1, 1-27-12
* Window Logic 1-27-13
=== [https://archive.org/details/SNESDevManual/book2/page/n408 Index for Book II]===
=== [https://archive.org/details/SNESDevManual/book2/page/n408 Index for Book II]===


[[Category:Books]]
[[Category:Books]]

Revision as of 02:31, 30 November 2023

According to the parts list, Book I has part number 24966 and Book II has part number 27457.

Book I

Section 1 - Approval Process

Chapter 1. NOA Licensed Software Approval Process - page 1-1-1

Chapter 2. Super NES Software Submission Requirements - page 1-2-1

Section 2 - Super NES Software

Chapter 1. Introduction - page 2-1-1

Chapter 2. Object (OBJ) - page 2-2-1

Chapter 3. Background (BG) - page 2-3-1

Chapter 4. Mosaic - page 2-4-1

Chapter 5. Rotation/Enlargement/Reduction - page 2-5-1

Chapter 6. Window (Window Mask) - page 2-6-1

Chapter 7. Main/Sub Screen - page 2-7-1

Chapter 8. CG Direct Select - page 2-8-1

Chapter 9. H-Pseudo 512 - page 2-9-1

Chapter 10. Complementary Multiplication (Signed Multiplication) - page 2-10-1

Chapter 11. H/V Counter Latch - page 2-11-1

Chapter 12. Offset Change - page 2-12-1

Chapter 13. Standard Controller - page 2-13-1

Chapter 14. Programmable I/O Port - page 2-14-1

Chapter 15. Absolute Multiplication/Division - page 2-15-1

Chapter 16. H/V Count Timer - page 2-16-1

Chapter 17. Direct Memory Access (DMA) - page 2-17-1

Chapter 18. Interlace - page 2-18-1

Chapter 19. H-512 Mode (BG Mode 5 & 6) - page 2-19-1

Chapter 20. OBJ 33's Lines Over & Priority Order - page 2-20-1

Chapter 21. CPU Clock and Memory Mapping - page 2-21-1

Chapter 22. Super NES Functional Operation - page 2-22-1

Chapter 23. System Flowchart - page 2-23-1

Chapter 24. Programming Cautions - page 2-24-1

Chapter 25. Documented Problems - page 2-25-1

Chapter 26. Register Clear (Initial Settings) - page 2-26-1

Chapter 27. PPU Registers - page 2-27-1

Chapter 28. CPU Registers - page 2-28-1

  • NMITIMEN Enable Flag for V-Blank, Timer Interrupt & Standard Controller Read - page 2-28-1
  • WRIO - Programmable I/O Port - page 2-28-1
  • WRMPYA / WRMPYB - Multiplier & Multiplicand by Multiplication - page 2-28-2
  • WRDIVL / WRDIVH / WRDIVB - Divisor & Dividend by Divide - page 2-28-2
  • HTIMEL / HTIMEH - H-Count Timer Settings - page 2-28-3
  • VTIMEL / VTIMEH - V-Count Timer Settings - page 2-28-3
  • MDMAEN - Channel Designation for General Purpose DMA & Trigger (Start) - page 2-28-4
  • HDMAEN - Channel Designation for H-DMA - page 2-28-5
  • MEMSEL - Access Cycle Designation in Memory - page 2-28-5
  • RDNMI - NMI Flag By V-Blank & Version Number - page 2-28-6
  • TIMEUP - IRQ Flag by H/V Count Timer - page 2-28-6
  • HVBJOY - H/V Blank Flag & Standard Controller Enable Flag - page 2-28-7
  • RDIO - Programmable I/O Port - page 2-28-7
  • RDDIVL / RDDIVH - Quotient of Divide Result - page 2-28-8
  • RDMPYL / RDMPYH - Product of Multiplication Result or Remainder of Divide Result - page 2-28-8
  • STD CNTRRL1L / 1H / 2L/2H/3L/3H/4L/4H - Data for Standard Controller - page 2-28-9

Section 3 - Super NES Sound

Chapter 1. SNES Sound Source Outline - page 3-1-1

Chapter 2. BRR (Bit Rate Reduction) - page 3-2-1

Chapter 3. I/O Ports - page 3-3-1

Chapter 4. Control Register - page 3-4-1

Chapter 5. Timers - page 3-5-1

Chapter 6. DSP Interface Register - page 3-6-1

Chapter 7. Register Used - page 3-7-1

Chapter 8. CPU Organization - page 3-8-1

Chapter 9. Sound Programming Cautions - page 3-9-1

Section 4 - Super NES CPU Data (missing)

  • Outline - page 4-1-1
  • Explanation of CPU Terminal Functions - page 4-2-1
  • Explanation of Functions - page 4-3-1
  • Addressing Mode - page 4-4-1
  • Command Set (Alphabetical Order) - page 4-5-1
  • Command Set (Matrix Display) - page 4-6-1
  • Cycles and Bytes of Addressing Modes - page 4-7-1
  • Differences Among 65C816, 65C02, and 6502 - page 4-8-1
  • Restrictions Upon Use & Application Information - page 4-9-1
  • Details of Command Functions - page 4-10-1
  • Description of Commands - page 4-11-1
  • AC Characteristics - page 4-12-1

Tables of Appendix

Appendix A. PPU Registers - page A-1

Appendix B. CPU Registers - page B-1

Appendix C SPC700 Commands - page C-1

Appendix D. Data Transfer Procedure - page D-1

Book II

Section 1 - Super Accelerator (SA-1)

Chapter 1. Super Accelerator System Functions - page 1-1-1

Chapter 2. Configuration of SA-1 - page 1-2-1

Chapter 3. Super Accelerator Memory Map - page 1-3-1

Chapter 4. SA-1 Internal Register Configuration - page 1-4-1

Chapter 5. Multi-Processor Processing - page 1-5-1

Chapter 6. Character Conversion - page 1-6-1

Chapter 7. Arithmetic Function - page 1-7-1

Chapter 8. Variable-Length Bit Processing - page 1-8-1

Chapter 9. DMA - page 1-9-1

Section 2 - Super FX

Chapter 1 Introduction to Super FX - page 2-1-1

Chapter 2 GSU Functional Operation - page 2-2-1

Chapter 3 Memory Mapping - page 2-3-1

Chapter 4 GSU Internal Register Configuration - page 2-4-1

Chapter 5 GSU Program Execution - page 2-5-1

Chapter 6 Instruction Execution - page 2-6-1

Chapter 7 Data Access - page 2-7-1

Chapter 8 GSU Special Functions - page 2-8-1

Chapter 9 Description of Instructions - page 2-9-1

Section 3 - DSP/DSP-1

Chapter 1 Introduction to DSP1 - page 3-1-1

Chapter 2 Command Summary - page 3-2-1

Chapter 3 Parameter Data Type - page 3-3-1

Chapter 4 Use of DSP1 - page 3-4-1

Chapter 5 Description of DSP1 Commands - page 3-5-1

Chapter 6 Math Functions and Equations - page 3-6-1

Section 4 - Accessories

Chapter 1. The Super NES Super Scope System - page 4-1-1

Chapter 2. Principles of the Super NES Super Scope - page 4-2-1

Chapter 3. Super NES Super Scope Functional Operation - page 4-3-1

Chapter 4. Super NES Super Scope Receiver Functions - page 4-4-1

Chapter 5. Graphics - page 4-5-1

Chapter 6. Super NES Mouse Specifications - page 4-6-1

Chapter 7. Using the Standard BIOS - page 4-7-1

Chapter 8 Programming Cautions - page 4-8-1

Chapter 9 MultiPlayer 5 Specifications - page 4-9-1

Chapter 10 MultiPlayer 5 Supplied BIOS - page 4-10-1

Supplemental Information

  • Super NES Parts List - page 1
  • Game Content Guidelines - page 3 (missing)
  • Guidelines Concerning Commercialism and Promotion of Licensee (missing)
  • Products or Services in Nintendo Licensed Games - page 5 (missing)
  • Super NES Video Timing Information - page 10 (missing)

Index for Book I

  • Absolute Addressing 1-17-4
  • Absolute Multiplication 1-15-1
  • Addition/Subtraction Screen 1-7-1
  • ADSR Mode 2-7-3
  • Audio Processing Unit 1-22-1
  • BG Mode 1-3-1, 1-27-3
  • Bit Rate Reduction 2-2-1
  • Brightness 1-27-1
  • BRR 2-2-1, 2-7-9
  • BRR Filter 2-2-1, 2-2-2
  • BRR Filter Number 2-2-1
  • BRR Format 2-2- 1
  • BRR Range 2-2-1, 2-2-2
  • CG-RAM 1-8-1, 1-27-11
  • Channels 1-17-1
  • Clock Speed 1-21-1
  • Color Constant 1-7-2
  • Color Constant Addition/Subtraction 1-7-5, 1-9-1
  • Color Generator RAM 1-22-2
  • Colors 1-2-1
  • Controller 1-13-1, 1-14-1
  • CPU Clock 1-21-1
  • Data Bank Register 3-3-2, 3-4-5, 3-4-8
  • Data Transfer 1-17-1
  • Direct Page Flag 2-8-7
  • Direct Register 3-4-8
  • Direct Select 1-27-16
  • Division 1-15-1
  • DMA 1-13-1, 1-17-1
  • DMA, General Purpose 1-13-1, 1-17-1
  • Echo Delay 2-7-9
  • Echo Enable 2-7-8
  • Echo Feed-Back 2-7-9
  • Echo Filter Coefficients 2-7-1
  • Echo Start Address 2-7-9
  • Emulation Mode 3-1-1, 3-2-1
  • Expanded Connector 1-13-1
  • ExtBG Mode 1-5-1, 1-27-19
  • External Latch Flag 1-27-22, 4-1-3
  • External Synchronization 1-27-19
  • Fixed Color Addition 1-6-1 G
  • Gain Mode 2-7-3
  • H-Blank 1-17-4
  • H-DMA 1-6-1, 1-12-1, 1-17-1
  • Horizontal Blanking 1-1-2
  • Indirect Addressing 1-17-4
  • Interface 1-14-1
  • Interlace 1-1-1, 1-1-2, 1-18-1
  • Interrupt 1-16-1
  • IPL ROM 2-1-1
  • Joy Controller Enable 1-28-1 M
  • Main Screen 1-7-1, 1-7-5
  • Mode 20 1-21-3
  • Mode 21 1-21-4
  • Mosaic 1-4-1, 1-27-3
  • Multiplication 1-27-20
  • Native Mode 3-2-1
  • NMI 1-13-1
  • OAM Priority Rotation 1-27-2
  • Object Attribute Memory 1-22-2, 1-27-2
  • Object Size 1-27-1
  • Pallets 1-2-1
  • Priority 1-2-1
  • Priority Order 1-20-2
  • Processor Status Register 3-9-2
  • Programmable I/O Port 1-14-1, 1-28-1
  • Program Bank Register 3-3-3, 3-4-7
  • Program Counter 3-3-3
  • Program Status Word 2-8-6
  • Resolution 1-3-1, 1-18-1 S
  • Screen Addition/Subtraction 1-6-1, 1-7-5, 1-9-1
  • Screen Repetition 1-27-4
  • Scroll 1-12-1
  • Scroll, Vertical Partial 1-12-1
  • Sony SPC700 2-8-1
  • Stack Pointer 3-3-3
  • Sub Screen 1-7-1, 1-7-5
  • Synchronization 1-16-1
  • Timer 1-16-1
  • Timer Enable 1-28-1
  • Transparency 1-7-2
  • Two’s Complement 1-10-1
  • Vertical Blanking 1-1-2 W
  • Window 1-6-1, 1-12-1, 1-27-12
  • Window Logic 1-27-13

Index for Book II

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