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According to the parts list, Book I has part number 24966 and Book II has part number 27457.

Book I

Section 1 - Approval Process

Chapter 1. NOA Licensed Software Approval Process - page 1-1-1

Chapter 2. Super NES Software Submission Requirements - page 1-2-1

Section 2 - Super NES Software

Chapter 1. Introduction - page 2-1-1

Chapter 2. Object (OBJ) - page 2-2-1

Chapter 3. Background (BG) - page 2-3-1

Chapter 4. Mosaic - page 2-4-1

Chapter 5. Rotation/Enlargement/Reduction - page 2-5-1

Chapter 6. Window (Window Mask) - page 2-6-1

Chapter 7. Main/Sub Screen - page 2-7-1

Chapter 8. CG Direct Select - page 2-8-1

Chapter 9. H-Pseudo 512 - page 2-9-1

Chapter 10. Complementary Multiplication (Signed Multiplication) - page 2-10-1

Chapter 11. H/V Counter Latch - page 2-11-1

Chapter 12. Offset Change - page 2-12-1

Chapter 13. Standard Controller - page 2-13-1

Chapter 14. Programmable I/O Port - page 2-14-1

Chapter 15. Absolute Multiplication/Division - page 2-15-1

Chapter 16. H/V Count Timer - page 2-16-1

Chapter 17. Direct Memory Access (DMA) - page 2-17-1

Chapter 18. Interlace - page 2-18-1

Chapter 19. H-512 Mode (BG Mode 5 & 6) - page 2-19-1

Chapter 20. OBJ 33's Lines Over & Priority Order - page 2-20-1

Chapter 21. CPU Clock and Memory Mapping - page 2-21-1

Chapter 22. Super NES Functional Operation - page 2-22-1

Chapter 23. System Flowchart - page 2-23-1

Chapter 24. Programming Cautions - page 2-24-1

Chapter 25. Documented Problems - page 2-25-1

Chapter 26. Register Clear (Initial Settings) - page 2-26-1

Chapter 27. PPU Registers - page 2-27-1

Chapter 28. CPU Registers - page 2-28-1

  • NMITIMEN Enable Flag for V-Blank, Timer Interrupt & Standard Controller Read - page 2-28-1
  • WRIO - Programmable I/O Port - page 2-28-1
  • WRMPYA / WRMPYB - Multiplier & Multiplicand by Multiplication - page 2-28-2
  • WRDIVL / WRDIVH / WRDIVB - Divisor & Dividend by Divide - page 2-28-2
  • HTIMEL / HTIMEH - H-Count Timer Settings - page 2-28-3
  • VTIMEL / VTIMEH - V-Count Timer Settings - page 2-28-3
  • MDMAEN - Channel Designation for General Purpose DMA & Trigger (Start) - page 2-28-4
  • HDMAEN - Channel Designation for H-DMA - page 2-28-5
  • MEMSEL - Access Cycle Designation in Memory - page 2-28-5
  • RDNMI - NMI Flag By V-Blank & Version Number - page 2-28-6
  • TIMEUP - IRQ Flag by H/V Count Timer - page 2-28-6
  • HVBJOY - H/V Blank Flag & Standard Controller Enable Flag - page 2-28-7
  • RDIO - Programmable I/O Port - page 2-28-7
  • RDDIVL / RDDIVH - Quotient of Divide Result - page 2-28-8
  • RDMPYL / RDMPYH - Product of Multiplication Result or Remainder of Divide Result - page 2-28-8
  • STD CNTRRL1L / 1H / 2L/2H/3L/3H/4L/4H - Data for Standard Controller - page 2-28-9

Section 3 - Super NES Sound

Chapter 1. SNES Sound Source Outline - page 3-1-1

Chapter 2. BRR (Bit Rate Reduction) - page 3-2-1

Chapter 3. I/O Ports - page 3-3-1

Chapter 4. Control Register - page 3-4-1

Chapter 5. Timers - page 3-5-1

Chapter 6. DSP Interface Register - page 3-6-1

Chapter 7. Register Used - page 3-7-1

Chapter 8. CPU Organization - page 3-8-1

Chapter 9. Sound Programming Cautions - page 3-9-1

Section 4 - Super NES CPU Data (missing)

  • Outline - page 4-1-1
  • Explanation of CPU Terminal Functions - page 4-2-1
  • Explanation of Functions - page 4-3-1
  • Addressing Mode - page 4-4-1
  • Command Set (Alphabetical Order) - page 4-5-1
  • Command Set (Matrix Display) - page 4-6-1
  • Cycles and Bytes of Addressing Modes - page 4-7-1
  • Differences Among 65C816, 65C02, and 6502 - page 4-8-1
  • Restrictions Upon Use & Application Information - page 4-9-1
  • Details of Command Functions - page 4-10-1
  • Description of Commands - page 4-11-1
  • AC Characteristics - page 4-12-1

Tables of Appendix

Appendix A. PPU Registers - page A-1

Appendix B. CPU Registers - page B-1

Appendix C SPC700 Commands - page C-1

Appendix D. Data Transfer Procedure - page D-1

Book II

Section 1 - Super Accelerator (SA-1)

Chapter 1. Super Accelerator System Functions - page 1-1-1

Chapter 2. Configuration of SA-1 - page 1-2-1

Chapter 3. Super Accelerator Memory Map - page 1-3-1

Chapter 4. SA-1 Internal Register Configuration - page 1-4-1

Chapter 5. Multi-Processor Processing - page 1-5-1

Chapter 6. Character Conversion - page 1-6-1

Chapter 7. Arithmetic Function - page 1-7-1

Chapter 8. Variable-Length Bit Processing - page 1-8-1

Chapter 9. DMA - page 1-9-1

Section 2 - Super FX

Chapter 1 Introduction to Super FX - page 2-1-1

Chapter 2 GSU Functional Operation - page 2-2-1

Chapter 3 Memory Mapping - page 2-3-1

Chapter 4 GSU Internal Register Configuration - page 2-4-1

Chapter 5 GSU Program Execution - page 2-5-1

Chapter 6 Instruction Execution - page 2-6-1

Chapter 7 Data Access - page 2-7-1

Chapter 8 GSU Special Functions - page 2-8-1

Chapter 9 Description of Instructions - page 2-9-1

Section 3 - DSP/DSP-1

Chapter 1 Introduction to DSP1 - page 3-1-1

Chapter 2 Command Summary - page 3-2-1

Chapter 3 Parameter Data Type - page 3-3-1

Chapter 4 Use of DSP1 - page 3-4-1

Chapter 5 Description of DSP1 Commands - page 3-5-1

Chapter 6 Math Functions and Equations - page 3-6-1

Section 4 - Accessories

Chapter 1. The Super NES Super Scope System - page 4-1-1

Chapter 2. Principles of the Super NES Super Scope - page 4-2-1

Chapter 3. Super NES Super Scope Functional Operation - page 4-3-1

Chapter 4. Super NES Super Scope Receiver Functions - page 4-4-1

Chapter 5. Graphics - page 4-5-1

Chapter 6. Super NES Mouse Specifications - page 4-6-1

Chapter 7. Using the Standard BIOS - page 4-7-1

Chapter 8 Programming Cautions - page 4-8-1

Chapter 9 MultiPlayer 5 Specifications - page 4-9-1

Chapter 10 MultiPlayer 5 Supplied BIOS - page 4-10-1

Supplemental Information

  • Super NES Parts List - page 1
  • Game Content Guidelines - page 3 (missing)
  • Guidelines Concerning Commercialism and Promotion of Licensee (missing)
  • Products or Services in Nintendo Licensed Games - page 5 (missing)
  • Super NES Video Timing Information - page 10 (missing)

Index for Book I

  • Absolute Addressing 1-17-4
  • Absolute Multiplication 1-15-1
  • Addition/Subtraction Screen 1-7-1
  • ADSR Mode 2-7-3
  • Audio Processing Unit 1-22-1
  • BG Mode 1-3-1, 1-27-3
  • Bit Rate Reduction 2-2-1
  • Brightness 1-27-1
  • BRR 2-2-1, 2-7-9
  • BRR Filter 2-2-1, 2-2-2
  • BRR Filter Number 2-2-1
  • BRR Format 2-2- 1
  • BRR Range 2-2-1, 2-2-2
  • CG-RAM 1-8-1, 1-27-11
  • Channels 1-17-1
  • Clock Speed 1-21-1
  • Color Constant 1-7-2
  • Color Constant Addition/Subtraction 1-7-5, 1-9-1
  • Color Generator RAM 1-22-2
  • Colors 1-2-1
  • Controller 1-13-1, 1-14-1
  • CPU Clock 1-21-1
  • Data Bank Register 3-3-2, 3-4-5, 3-4-8
  • Data Transfer 1-17-1
  • Direct Page Flag 2-8-7
  • Direct Register 3-4-8
  • Direct Select 1-27-16
  • Division 1-15-1
  • DMA 1-13-1, 1-17-1
  • DMA, General Purpose 1-13-1, 1-17-1
  • Echo Delay 2-7-9
  • Echo Enable 2-7-8
  • Echo Feed-Back 2-7-9
  • Echo Filter Coefficients 2-7-1
  • Echo Start Address 2-7-9
  • Emulation Mode 3-1-1, 3-2-1
  • Expanded Connector 1-13-1
  • ExtBG Mode 1-5-1, 1-27-19
  • External Latch Flag 1-27-22, 4-1-3
  • External Synchronization 1-27-19
  • Fixed Color Addition 1-6-1 G
  • Gain Mode 2-7-3
  • H-Blank 1-17-4
  • H-DMA 1-6-1, 1-12-1, 1-17-1
  • Horizontal Blanking 1-1-2
  • Indirect Addressing 1-17-4
  • Interface 1-14-1
  • Interlace 1-1-1, 1-1-2, 1-18-1
  • Interrupt 1-16-1
  • IPL ROM 2-1-1
  • Joy Controller Enable 1-28-1 M
  • Main Screen 1-7-1, 1-7-5
  • Mode 20 1-21-3
  • Mode 21 1-21-4
  • Mosaic 1-4-1, 1-27-3
  • Multiplication 1-27-20
  • Native Mode 3-2-1
  • NMI 1-13-1
  • OAM Priority Rotation 1-27-2
  • Object Attribute Memory 1-22-2, 1-27-2
  • Object Size 1-27-1
  • Pallets 1-2-1
  • Priority 1-2-1
  • Priority Order 1-20-2
  • Processor Status Register 3-9-2
  • Programmable I/O Port 1-14-1, 1-28-1
  • Program Bank Register 3-3-3, 3-4-7
  • Program Counter 3-3-3
  • Program Status Word 2-8-6
  • Resolution 1-3-1, 1-18-1 S
  • Screen Addition/Subtraction 1-6-1, 1-7-5, 1-9-1
  • Screen Repetition 1-27-4
  • Scroll 1-12-1
  • Scroll, Vertical Partial 1-12-1
  • Sony SPC700 2-8-1
  • Stack Pointer 3-3-3
  • Sub Screen 1-7-1, 1-7-5
  • Synchronization 1-16-1
  • Timer 1-16-1
  • Timer Enable 1-28-1
  • Transparency 1-7-2
  • Two’s Complement 1-10-1
  • Vertical Blanking 1-1-2 W
  • Window 1-6-1, 1-12-1, 1-27-12
  • Window Logic 1-27-13

Index for Book II

COMMANDS/INSTRUCTIONS

  • ADC Rn 2-2-6, 2-9-3
  • ADC #n 2-2-6, 2-9-4
  • ADD Rn 2-2-6, 2-9-5
  • ADD #n 2-2-6, 2-9-6
  • ALT I 2-2-8, 2-9-7
  • ALT2 2-2-8, 2-9-8
  • ALT3 2-2-8, 2-9-9
  • AND Rn 2-2-7, 2-9-10
  • AND #n 2-2-7, 2-9-11
  • ASR 2-2-7, 2-9-1
  • ATTITUDE 3-5-22
  • BCC e 2-2-7, 2-9-14
  • BCSe 2-2-7, 2-9-16
  • BEQe 2-2-7, 2-9-18
  • BGE e 2-2-7, 2-9-20
  • BIC Rn 2-2-7, 2-9-22
  • BIC #n 2-2-7, 2-9-23
  • BLT e 2-2-7, 2-9-24
  • BMI e 2-2-7, 2-9-26
  • BNE e 2-2-7, 2-9-28
  • BPL e 2-2-7, 2-9-30
  • BRA e 2-2-7, 2-9-32
  • BVC e 2-2-7, 2-9-34
  • BVS e 2-2-7, 2-9-36
  • CACHE 2-2-8, 2-9-38
  • CMODE 2-2-7, 2-9-39
  • CMP Rn 2-2-6, 2-9-41
  • COLOR 2-2-7, 2-9-42
  • DEC Rn 2-2-6, 2-9-43
  • DISTANCE 3-5-7
  • DIV2 2-2-6, 2-9-44
  • FMULT 2-2-6, 2-9-46
  • FROM Rn 2-2-8, 2-9-48
  • GETB 2-2-6, 2-9-49
  • GETBH 2-2-6, 2-9-51
  • GETBL 2-2-6, 2-9-53
  • GETBS 2-2-6, 2-9-55
  • GETC 2-2-6, 2-9-57
  • GYRATE 3-5-31
  • HIB 2-2-7, 2-9-58
  • IBT Rn, #pp 2-2-6, 2-9-60
  • INC Rn 2-2-6, 2-9-61
  • INVERSE 3-5-2
  • LEA Rn, xx 2-2-8, 2-9-67
  • LINK #n 2-2-7, 2-9-68
  • LJMP Rn 2-2-7, 2-9-69
  • LM Rn, (xx) 2-2-6, 2-9-70
  • LMS Rn, (yy) 2-2-6, 2-9-71
  • LMULT 2-2-6, 2-9-73
  • LOB 2-2-7, 2-9-75
  • LOOP 2-2-7, 2-9-77
  • LSR 2-2-7, 2-9-78
  • MERGE 2-2-7, 2-9-79
  • MOVE Rn, Rn’ 2-2-8, 2-9-81
  • MOVE Rn, #xx 2-2-8, 2-9-82
  • MOVE Rn, (xx) 2-2-8, 2-9-83
  • MOVE (xx), Rn 2-2-8, 2-9-85
  • MOVEB Rn, (Rn’) 2-2-8, 2-9-87
  • MOVEB (Rn’), Rn 2-2-8, 2-9-88
  • MOVES Rn, Rn’ 2-2-8, 2-9-89
  • MOVEW Rn,(Rn’) 2-2-8, 2-9-90
  • MOVEW (Rn’), Rn 2-2-8, 2-9-91
  • MULT Rn 2-2-6, 2-9-93
  • MULT #n 2-2-6, 2-9-94
  • MULTIPLY 3-5-1
  • NOP 2-2-8, 2-9-95
  • NOT 2-2-7, 2-9-96
  • OBJECTIVE 3-5-25
  • OR Rn 2-2-7, 2-9-97
  • OR #n 2-2-7, 2-9-99
  • PARAMETER 3-5-12
  • PLOT 2-2-7, 2-9-100
  • POLAR 3-5-9
  • PROJECT 3-5-18
  • RADIUS 3-5-4
  • RAMB 2-2-7, 2-9-101
  • RANGE 3-5-6
  • RASTER 3-5-15
  • ROL 2-2-7, 2-9-102
  • ROMB 2-2-7,2-9-104
  • ROR 2-2-7, 2-9-105
  • ROTATE 3-5-8
  • RPIX 2-2-7, 2-9-107
  • SBC Rn 2-2-6, 2-9-108
  • SBK 2-2-6, 2-9-109
  • SCALAR 3-5-29
  • SEX 2-2-7, 2-9-110
  • SM (xx), Rn 2-2-6, 2-9-112
  • SMS (yy), Rn 2-2-6, 2-9-113
  • STB(Rn) 2-2-6, 2-9-115
  • STOP 2-2-8, 2-9-116
  • STW (Rn) 2-2-6, 2-9-117
  • SUB Rn 2-2-6, 2-9-118
  • SUB #n 2-2-6, 2-9-119
  • SUBJECTIVE 3-5-27
  • SWAP 2-2-7, 2-9-120
  • TARGET 3-5-20
  • TO Rn 2-2-8, 2-9-121
  • Triangle 3-5-3
  • UMULT Rn 2-2-6, 2-9-122
  • UMULT #n 2-2-6, 2-9-123
  • WITH Rn 2-2-8, 2-9-124
  • XOR Rn 2-2-7, 2-9-125
  • XOR#n 2-2-7, 2-9-126

SUBJECT - Alphabetical Listing

  • Accelerator Mode 1-5-6
  • Access Modes 2-4-8, 2-5-2, 2-5-4, 2-6-1
  • ADC #n 2-2-6, 2-9-4
  • ADC Rn 2-2-6, 2-9-3
  • ADD #n 2-2-6, 2-9-6
  • ADD Rn 2-2-6, 2-9-5
  • ALT1 2-2-8, 2-9-7
  • ALT2 2-2-8, 2-9-8
  • ALT3 2-2-8, 2-9-9
  • AND #n 2-2-7, 2-9-1 1
  • AND Rn 2-2-7, 2-9-10
  • ASR 2-2-7, 2-9-12
  • Attitude 2-5-10, 2-5-22, 2-5-24, 2-5-25, 2-5-27, 2-5-28, 2-5-29, 2-5-31, 2-5-32, 2-5-33
  • Auto-increment Mode 1-8-3
  • Barrel Shift 1-8-4, 1-8-5
  • BCCe 2-2-7, 2-9-14
  • BCSe 2-2-7, 2-9-16
  • BEQe 2-2-7, 2-9-18
  • BGE e 2-2-7, 2-9-20
  • BIC #n 2-2-7, 2-9-23
  • BIC Rn 2-2-7, 2-9-22
  • Bitmap 1-8-14
  • Bitmap Access 1-6-3
  • Bitmap Emulation 1-8-1
  • Bitmap Format 1-6-1
  • BLT e 2-2-7, 2-9-24
  • BMI e 2-2-7, 2-9-26
  • BNE e 2-2-7, 2-9-28
  • BPL e 2-2-7, 2-9-30
  • BRA e 2-2-7, 2-9-32
  • Bulk Processing 2-7-4
  • BVC e 2-2-7, 2-9-34
  • BVS e 2-2-7, 2-9-36
  • BW-RAM 1-1-1, 1-1-2, 1-1-3, 1-1-4, 1-2-2, 1-2-4, 1-6-6
  • Cache 2-6-1, 2-8-4, 2-8-5, 2-8-6, 2-8-7, 2-9-38
  • Cache RAM 2-6-1, 2-6-2, 2-8-8
  • Character Conversion 1 1-6-1, 1-6-7, 1-6-8
  • Character Conversion 2 1-6-2, 1-6-10, 1-6-11
  • CMODE 2-8-1, 2-8-9, 2-8-11, 2-8-12, 2-9-39
  • CMP Rn 2-9-41
  • Color 2-8-1, 2-8-4, 2-8-6, 2-8-10, 2-8-11, 2-8-12, 2-8-13, 2-9-41, 2-9-42
  • COLR 2-2-3, 2-2-5, 2-4-9, 2-8-4, 2-8-10, 2-8-11,2-8-12, 2-8-13
  • Cumulative Arithmetic 1-1-2
  • Cumulative Sum 1-7-1, 1-7-3
  • DEC Rn 2-2-6, 2-9-43
  • Distance 3-5-4, 3-5-7
  • Dither 2-4-9, 2-8-9, 2-8-10, 2-8-11
  • DIV2 2-2-6, 2-9-44
  • Division 1-7-1, 1-7-2
  • DMA 1-9-1
  • External Latch 4-1-4
  • External Latch Flag 4-1-3
  • Fixed Mode 1-8-2
  • FMULT 2-2-6, 2-4-1, 2-8-16, 2-8-17, 2-9-46
  • FROM 2-6-4, 2-6-6, 2-6-7, 2-6-11, 2-7-1, 2-7-2, 2-7-3, 2-7-4, 2-8-10, 2-8-11
  • FROM Rn 2-2-8, 2-9-48
  • GETB 2-2-6, 2-9-49
  • GETBH 2-2-6, 2-9-51
  • GETBL 2-2-6, 2-9-53
  • GETBS 2-2-6, 2-9-55
  • GETC 2-2-6, 2-8-1, 2-8-4, 2-8-9, 2-8-12, 2-8-13, 2-9-57
  • Gyrate 3-5-31
  • H Counter 4-1-4
  • HIB 2-2-7, 2-9-58
  • Horizontal Counter Latch 4-1-3
  • HV Timer 1-1-2, 1-10-1
  • IBT Rn, #pp 2-2-6, 2-9-60
  • INC Rn 2-2-6, 2-9-61
  • Inverse 3-5-2
  • I-RAM 1-1-1, 1-1-3, 1-1-4, 1-2-2, 1-2-5, 1-3-5
  • IWT Rn, #xx 2-2-6, 2-9-62
  • JMP Rn 2-2-7, 2-4-3, 2-9-63
  • LDB (Rn) 2-2-7, 2-9-64
  • LDW (Rn) 2-2-7, 2-9-66
  • LEA Rn, xx 2-2-8, 2-9-67
  • Linear Timer 1-10-1
  • LINK #n 2-2-7, 2-9-68
  • LJMP Rn 2-2-7, 2-9-69
  • LM Rn, (xx) 2-2-7, 2-9-70
  • LMSRn, (yy) 2-2-7, 2-9-71
  • LMULT 2-2-6, 2-4-1, 2-8-16, 2-8-17, 2-9-73
  • LOB 2-2-7, 2-9-75
  • LOOP 2-2-7, 2-9-77
  • LSR 2-2-7, 2-9-78
  • Masked Interrupt 1-5-3
  • MERGE 2-2-7, 2-9-79 Message 1-5-3
  • Mixed Processing Mode 1-5-8
  • MOVE (xx), Rn 2-2-8, 2-9-85
  • MOVE Rn, #xx 2-2-8, 2-9-82
  • MOVE Rn, (xx) 2-2-8, 2-9-83
  • MOVE Rn, Rn’ 2-2-6, 2-9-81
  • MOVEB (Rn’), Rn 2-2-8, 2-9-88
  • MOVEB Rn, (Rn’) 2-2-8, 2-9-87
  • MOVES Rn, Rn’ 2-2-6, 2-9-89
  • MOVEW (Rn’), Rn 2-2-8, 2-9-91
  • MOVEW Rn,(Rn’) 2-2-8, 2-9-90
  • MULT #n 2-2-6, 2-8-16, 2-9-94
  • MULT Rn 2-2-6, 2-8-16, 2-9-93
  • Multiplication 1-7-1, 1-7-2
  • Multiply 3-5-1
  • NOP 2-2-8, 2-6-2, 2-6-3, 2-6-4, 2-6-5, 2-6-7, 2-6-9, 2-8-10, 2-9-95
  • Normal Color 2-8-1 1
  • Normal DMA 1-9-2
  • NOT 2-2-8, 2-9-96
  • Parallel Processing Mode 1-5-7
  • Parameter 3-3-1, 3-5-1
  • Pipeline Processing 2-6-1, 2-6-3, 2-6-5
  • Pixel Cache 2-8-4, 2-8-5, 2-8-6, 2-8-7, 2-8-9
  • Plot 2-2-7, 2-4-1, 2-4-8, 2-4-9, 2-8-1, 2-8-4, 28-5, 2-8-6, 2-8-7, 2-8-8, 2-8-9, 2-8-10, 28-11,2-8-13, 2-9-100
  • Polar 3-5-9
  • Project 3-5-10, 3-5-12, 3-5-13, 3-5-14, 3-5-15, 3-5-17, 3-5-18, 3-5-19, 3-5-20, 3-5-28
  • Radius 3-5-3, 3-5-4, 3-5-6, 3-5-7, 3-5-30
  • RAMB 2-2-7, 2-4-6, 2-7-3, 2-9-101
  • RAN 2-4-8, 2-5-2, 2-5-4, 2-6-1
  • Range 3-5-6, 3-5-30
  • Raster 3-2-1, 3-5-12, 3-5-13, 3-5-15, 3-5-16
  • Register Prefix 2-6-6
  • ROL 2-2-7, 2-9-102
  • ROMB 2-2-7, 2-4-5, 2-7-1, 2-9-104
  • RON 2-4-8, 2-5-2, 2-5-4, 2-6-1
  • ROR 2-2-7, 2-9-105
  • Rotate 3-5-8, 3-5-23
  • RPIX 2-2-7, 2-8-6, 2-8-9, 2-8-12, 2-9-107
  • Objective 3-5-22, 3-5-25, 3-5-26
  • OBJ Rotation 2-8-1 1
  • OBJ Scaling 2-8-11
  • OR #n 2-2-7, 2-9-99
  • OR Rn 2-2-7, 2-9-97
  • SBC Rn 2-2-6, 2-9-108
  • XOR #n 2-2-7, 2-9-126
  • SBK 2-2-6, 2-9- 1 09
  • XOR Rn 2-2-7, 2-9- 1 25
  • SBK Instruction 2-7-2, 2-7-4, 2-7-5
  • Scalar 3-5-29
  • SCR 2-8-14
  • SEX 2-2-7, 2-9-1 10
  • Shared Memory 1-5-4
  • SM (xx), Rn 2-2-6, 2-9-112
  • SMS (yy), Rn 2-2-6, 2-9-113
  • Sprite Rotation 2-8- 1 1
  • Sprite Scaling 2-8-1 1
  • STB(Rn) 2-2-6, 2-9-115
  • STOP 2-2-8, 2-9-116
  • STW (Rn) 2-2-6, 2-9-117
  • SUB #n 2-2-6, 2-9-119
  • SUB Rn 2-2-6, 2-9-118
  • Subjective 3-5-22, 3-5-27
  • Super MMC 1-1-1, 1-3-3, 1-3-4
  • SWAP 2-2-7, 2-9-120
  • Target 3-5-17, 3-5-20, 3-5-21
  • TO 2-6-2, 2-6-4, 2-6-6, 2-6-7
  • TO Rn 2-2-8, 2-9-121
  • Transparent 2-8-9, 2-8-10, 2-8-1 1, 2-8-13
  • Triangle 3-5-3
  • UMULT #n 2-2-6, 2-8-16, 2-9-123
  • UMULT Rn 2-2-6, 2-8-16, 2-9-122
  • V Counter 4- 1-4
  • Variable-length Data 1-8-1, 1-8-4
  • Vector Switching 1-5-4
  • Vertical Counter Latch 4-1-3
  • Virtual VRAM 1-1-2
  • WITH 2-6-4, 2-6-6, 2-6-7
  • WITH Rn 2-2-8, 2-9-124
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