We've just updated MediaWiki and its underlying software. If anything doesn't look or work quite right, please mention it to us. --RanAS

Official Documentation Quick Links: Difference between revisions

From SnesLab
Jump to: navigation, search
(added missing section 4)
Line 162: Line 162:
==== [https://archive.org/details/SNESDevManual/book1/page/n179 Chapter 8. CPU Organization] - page 3-8-1====
==== [https://archive.org/details/SNESDevManual/book1/page/n179 Chapter 8. CPU Organization] - page 3-8-1====
==== [https://archive.org/details/SNESDevManual/book1/page/n188 Chapter 9. Sound Programming Cautions] - page 3-9-1====
==== [https://archive.org/details/SNESDevManual/book1/page/n188 Chapter 9. Sound Programming Cautions] - page 3-9-1====
=== Section 4 - Super NES CPU Data (missing) ===
* Outline - page 4-1-1
* Explanation of CPU Terminal Functions - page 4-2-1
* Explanation of Functions - page 4-3-1
* Addressing Mode - page 4-4-1
* Command Set (Alphabetical Order) - page 4-5-1
* Command Set (Matrix Display) - page 4-6-1
* Cycles and Bytes of Addressing Modes - page 4-7-1
* Differences Among 65C816, 65C02, and 6502 - page 4-8-1
* Restrictions Upon Use & Application Information - page 4-9-1
* Details of Command Functions - page 4-10-1
* Description of Commands - page 4-11-1
* AC Characteristics - page 4-12-1


=== Tables of Appendix ===
=== Tables of Appendix ===

Revision as of 19:14, 21 July 2023

According to the parts list, Book I has part number 24966 and Book II has part number 27457.

Book I

Section 1 - Approval Process

Chapter 1. NOA Licensed Software Approval Process - page 1-1-1

Chapter 2. Super NES Software Submission Requirements - page 1-2-1

Section 2 - Super NES Software

Chapter 1. Introduction - page 2-1-1

Chapter 2. Object (OBJ) - page 2-2-1

Chapter 3. Background (BG) - page 2-3-1

Chapter 4. Mosaic - page 2-4-1

Chapter 5. Rotation/Enlargement/Reduction - page 2-5-1

Chapter 6. Window (Window Mask) - page 2-6-1

Chapter 7. Main/Sub Screen - page 2-7-1

Chapter 8. CG Direct Select - page 2-8-1

Chapter 9. H-Pseudo 512 - page 2-9-1

Chapter 10. Complementary Multiplication (Signed Multiplication) - page 2-10-1

Chapter 11. H/V Counter Latch - page 2-11-1

Chapter 12. Offset Change - page 2-12-1

Chapter 13. Standard Controller - page 2-13-1

Chapter 14. Programmable I/O Port - page 2-14-1

Chapter 15. Absolute Multiplication/Division - page 2-15-1

Chapter 16. H/V Count Timer - page 2-16-1

Chapter 17. Direct Memory Access (DMA) - page 2-17-1

Chapter 18. Interlace - page 2-18-1

Chapter 19. H-512 Mode (BG Mode 5 & 6) - page 2-19-1

Chapter 20. OBJ 33's Lines Over & Priority Order - page 2-20-1

Chapter 21. CPU Clock and Memory Mapping - page 2-21-1

Chapter 22. Super NES Functional Operation - page 2-22-1

Chapter 23. System Flowchart - page 2-23-1

Chapter 24. Programming Cautions - page 2-24-1

Chapter 25. Documented Problems - page 2-25-1

Chapter 26. Register Clear (Initial Settings) - page 2-26-1

Chapter 27. PPU Registers - page 2-27-1

Chapter 28. CPU Registers - page 2-28-1

  • NMITIMEN Enable Flag for V-Blank, Timer Interrupt & Standard Controller Read - page 2-28-1
  • WRIO - Programmable I/O Port - page 2-28-1
  • WRMPYA / WRMPYB - Multiplier & Multiplicand by Multiplication - page 2-28-2
  • WRDIVL / WRDIVH / WRDIVB - Divisor & Dividend by Divide - page 2-28-2
  • HTIMEL / HTIMEH - H-Count Timer Settings - page 2-28-3
  • VTIMEL / VTIMEH - V-Count Timer Settings - page 2-28-3
  • MDMAEN - Channel Designation for General Purpose DMA & Trigger (Start) - page 2-28-4
  • HDMAEN - Channel Designation for H-DMA - page 2-28-5
  • MEMSEL - Access Cycle Designation in Memory - page 2-28-5
  • RDNMI - NMI Flag By V-Blank & Version Number - page 2-28-6
  • TIMEUP - IRQ Flag by H/V Count Timer - page 2-28-6
  • HVBJOY - H/V Blank Flag & Standard Controller Enable Flag - page 2-28-7
  • RDIO - Programmable I/O Port - page 2-28-7
  • RDDIVL / RDDIVH - Quotient of Divide Result - page 2-28-8
  • RDMPYL / RDMPYH - Product of Multiplication Result or Remainder of Divide Result - page 2-28-8
  • STD CNTRRL1L / 1H / 2L/2H/3L/3H/4L/4H - Data for Standard Controller - page 2-28-9

Section 3 - Super NES Sound

Chapter 1. SNES Sound Source Outline - page 3-1-1

Chapter 2. BRR (Bit Rate Reduction) - page 3-2-1

Chapter 3. I/O Ports - page 3-3-1

Chapter 4. Control Register - page 3-4-1

Chapter 5. Timers - page 3-5-1

Chapter 6. DSP Interface Register - page 3-6-1

Chapter 7. Register Used - page 3-7-1

Chapter 8. CPU Organization - page 3-8-1

Chapter 9. Sound Programming Cautions - page 3-9-1

Section 4 - Super NES CPU Data (missing)

  • Outline - page 4-1-1
  • Explanation of CPU Terminal Functions - page 4-2-1
  • Explanation of Functions - page 4-3-1
  • Addressing Mode - page 4-4-1
  • Command Set (Alphabetical Order) - page 4-5-1
  • Command Set (Matrix Display) - page 4-6-1
  • Cycles and Bytes of Addressing Modes - page 4-7-1
  • Differences Among 65C816, 65C02, and 6502 - page 4-8-1
  • Restrictions Upon Use & Application Information - page 4-9-1
  • Details of Command Functions - page 4-10-1
  • Description of Commands - page 4-11-1
  • AC Characteristics - page 4-12-1

Tables of Appendix

Appendix A. PPU Registers - page A-1

Appendix B. CPU Registers - page B-1

Appendix C SPC700 Commands - page C-1

Appendix D. Data Transfer Procedure - page D-1

Book II

Section 1 - Super Accelerator (SA-1)

Chapter 1. Super Accelerator System Functions - page 1-1-1

Chapter 2. Configuration of SA-1 - page 1-2-1

Chapter 3. Super Accelerator Memory Map - page 1-3-1

Chapter 4. SA-1 Internal Register Configuration - page 1-4-1

Chapter 5. Multi-Processor Processing - page 1-5-1

Chapter 6. Character Conversion - page 1-6-1

Chapter 7. Arithmetic Function - page 1-7-1

Chapter 8. Variable-Length Bit Processing - page 1-8-1

Chapter 9. DMA - page 1-9-1

Section 2 - Super FX

Chapter 1 Introduction to Super FX - page 2-1-1

Chapter 2 GSU Functional Operation - page 2-2-1

Chapter 3 Memory Mapping - page 2-3-1

Chapter 4 GSU Internal Register Configuration - page 2-4-1

Chapter 5 GSU Program Execution - page 2-5-1

Chapter 6 Instruction Execution - page 2-6-1

Chapter 7 Data Access - page 2-7-1

Chapter 8 GSU Special Functions - page 2-8-1

Chapter 9 Description of Instructions - page 2-9-1

Section 3 - DSP/DSP-1

Chapter 1 Introduction to DSP1 - page 3-1-1

Chapter 2 Command Summary - page 3-2-1

Chapter 3 Parameter Data Type - page 3-3-1

Chapter 4 Use of DSP1 - page 3-4-1

Chapter 5 Description of DSP1 Commands - page 3-5-1

Chapter 6 Math Functions and Equations - page 3-6-1

Section 4 - Accessories

Chapter 1. The Super NES Super Scope System - page 4-1-1

Chapter 2. Principles of the Super NES Super Scope - page 4-2-1

Chapter 3. Super NES Super Scope Functional Operation - page 4-3-1

Chapter 4. Super NES Super Scope Receiver Functions - page 4-4-1

Chapter 5. Graphics - page 4-5-1

Chapter 6. Super NES Mouse Specifications - page 4-6-1

Chapter 7. Using the Standard BIOS - page 4-7-1

Chapter 8 Programming Cautions - page 4-8-1

Chapter 9 MultiPlayer 5 Specifications - page 4-9-1

Chapter 10 MultiPlayer 5 Supplied BIOS - page 4-10-1

Supplemental Information

  • Super NES Parts List - page 1
  • Game Content Guidelines - page 3 (missing)
  • Guidelines Concerning Commercialism and Promotion of Licensee (missing)
  • Products or Services in Nintendo Licensed Games - page 5 (missing)
  • Super NES Video Timing Information - page 10 (missing)

Index for Book I

Index for Book II