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From SnesLab
According to the parts list, Book I has part number 24966 and Book II has part number 27457.
Book I
- Table of Contents - page i
- List of Figures - page v
- List of Tables - page ix
- Preface - page 1
- Confidentiality Agreement - page 2
Section 1 - Approval Process
Chapter 1. NOA Licensed Software Approval Process - page 1-1-1
- Authorized Software Developer Requirements - page 1-1-2
Chapter 2. Super NES Software Submission Requirements - page 1-2-1
- Software Verification - page 1-2-3
- Software Submission Check List - page 1-2-6
- This Page Intentionally Left Blank - page 1-2-7
- Super NES Software Specification - page 1-2-9
- Instructions for Super NES Software Specification - page 1-2-10
- Character Code List for Game Title Registration - page 1-2-13
- ROM Registration Data Specification - page 1-2-14
- Description of ROM Registration Data Specification - page 1-2-15
- Data Storage on Floppy Disk - page 1-2-22
- Super NES Cartridge PCB List - page 1-2-23
- SHVC Cartridge List (21 Map, Production Type) - page 1-2-38
- This Page Intentionally Left Blank - page 1-2-39
- Price Quote Request for Super NES Cartridge - page 1-2-40
Section 2 - Super NES Software
Chapter 1. Introduction - page 2-1-1
- Super NES Display - page 2-1-2
Chapter 2. Object (OBJ) - page 2-2-1
- Setting Example - page 2-2-2
Chapter 3. Background (BG) - page 2-3-1
- Setting Example - page 2-3-2
Chapter 4. Mosaic - page 2-4-1
Chapter 5. Rotation/Enlargement/Reduction - page 2-5-1
- Setting Example - page 2-5-2
Chapter 6. Window (Window Mask) - page 2-6-1
Chapter 7. Main/Sub Screen - page 2-7-1
- Screen Addition/Subtraction - page 2-7-2
- Setting Example - page 2-7-3
- Color Constant Addition/Subtraction - page 2-7-4
- Color Window - page 2-7-5
Chapter 8. CG Direct Select - page 2-8-1
Chapter 9. H-Pseudo 512 - page 2-9-1
Chapter 10. Complementary Multiplication (Signed Multiplication) - page 2-10-1
Chapter 11. H/V Counter Latch - page 2-11-1
Chapter 12. Offset Change - page 2-12-1
Chapter 13. Standard Controller - page 2-13-1
- Setting Example - page 2-13-2
Chapter 14. Programmable I/O Port - page 2-14-1
Chapter 15. Absolute Multiplication/Division - page 2-15-1
Chapter 16. H/V Count Timer - page 2-16-1
Chapter 17. Direct Memory Access (DMA) - page 2-17-1
- Setting Example - page 2-17-3
Chapter 18. Interlace - page 2-18-1
Chapter 19. H-512 Mode (BG Mode 5 & 6) - page 2-19-1
Chapter 20. OBJ 33's Lines Over & Priority Order - page 2-20-1
- Priority Order Shifting - page 2-20-2
Chapter 21. CPU Clock and Memory Mapping - page 2-21-1
- Super NES CPU Memory Map - page 2-21-2
- Super NES Memory Map (Mode 20) - page 2-21-3
- Super NES Memory Map (Mode 21) - page 2-21-4
- Super NES Memory Map (Mode 25, ROM Size Greater than 32 Mbits only) - page 2-21-5
Chapter 22. Super NES Functional Operation - page 2-22-1
- Super NES Functional Block Diagram - page 2-22-2
Chapter 23. System Flowchart - page 2-23-1
Chapter 24. Programming Cautions - page 2-24-1
- Edge Detection - page 2-24-5
- Sample Program - page 2-24-6
- Alternate Method - page 2-24-7
- This Page Intentionally Left Blank - page 2-24-8
Chapter 25. Documented Problems - page 2-25-1
- Problem 2 - page 2-25-2
Chapter 26. Register Clear (Initial Settings) - page 2-26-1
Chapter 27. PPU Registers - page 2-27-1
- INIDISP - Initial Settings for Screen - page 2-27-1
- OBJSEL - Object Size & Object Data Area Designation - page 2-27-1
- OAMADDL / OAMADDH - Address for Accessing OAM - page 2-27-2
- OAM DATA - Data for OAM write - page 2-27-2
- BG MODE aka BGMODE - Background Mode & Character Size Settings - page 2-27-3
- MOSAIC - Size & Screen Designation for Mosaic Display - page 2-27-3
- BG1SC / BG2SC / BG3SC / BG4SC - Address for Storing SC-Data of each BG & SC Size Designation - page 2-27-4
- BG1NBA / BG34NBA - BG Character Area Designation - page 2-27-5
- BG1H0FS / BG1V0FS - H/V Scroll Value Designation for BG-1 - page 2-27-5
- BG2H0FS / BG2V0FS / BG3H0FS / BG3V0FS / BG40FS / BG4V0FS - H/V Scroll Value Designation for BG-2,3,4 page 2-27-6
- VMAINC - VRAM Address Increment Value Designation - page 2-27-6
- VMADDL / VMADDH - Address for VRAM Read & Write - page 2-27-7
- VMDATAL / VMDATAH - Data for VRAM Write - page 2-27-7
- M7SEL - Initial Setting in Screen Mode-7 - page 2-27-8
- M7A / M7B / M7C / M7D / M7X / M7Y - page 2-27-9
- CGADD / CGDATA - Address for CG-RAM Read and Write - page 2-27-11
- W12SEL / W34SEL / WOBJSEL - Window Mask Settings - page 2-27-12
- WH0 / WH1 / WH2 / WH3 - Window Position Designation - page 2-27-12
- WBGLOG / WOBJLOG - Mask Logic Settings for Window-1 & 2 on Each Screen - page 2-27-13
- TM - Main Screen Designation - page 2-27-14
- TS - Sub Screen Designation - page 2-27-14
- TMW - Window Mask Designation for Main Screen - page 2-27-15
- TSW - Window Mask Designation for Sub Screen - page 2-27-15
- CGSWEL - Initial Settings for Fixed Color Addition or Screen Addition - page 2-27-16
- CGADSUB - page 2-27-17
- COLDATA - Fixed Color Data for Fixed Color Addition/Subtraction - page 2-27-18
- SETINI - Screen Initial Setting - page 2-27-19
- MPYL / MPYM / MPYH - Multiplication Result - page 2-27-20
- SLHV - Software Latch for H/V Counter - page 2-27-20
- OAMDATA - Read Data from OAM - page 2-27-21
- VMDATAL / VMDATAH - Read Data from VRAM - page 2-27-21
- CGDATA - Read Data from CG-RAM - page 2-27-22
- OPHCT / OPVCT - H/V Counter Data by External or Software Latch - page 2-27-22
- STAT77 / STAT78 - PPU Status Flag & Version Number - page 2-27-23
- APUIO0 / APUIO1 / APUIO2 / APUIO3 - Communication Port with APU - page 2-27-24
- WMDATA - Data to consecutively read from and write to WRAM - page 2-27-25
- WMADDL / WMADDM / WMADDH - Address to consecutively read and write WRAM - page 2-27-25
Chapter 28. CPU Registers - page 2-28-1
- NMITIMEN Enable Flag for V-Blank, Timer Interrupt & Standard Controller Read - page 2-28-1
- WRIO - Programmable I/O Port - page 2-28-1
- WRMPYA / WRMPYB - Multiplier & Multiplicand by Multiplication - page 2-28-2
- WRDIVL / WRDIVH / WRDIVB - Divisor & Dividend by Divide - page 2-28-2
- HTIMEL / HTIMEH - H-Count Timer Settings - page 2-28-3
- VTIMEL / VTIMEH - V-Count Timer Settings - page 2-28-3
- MDMAEN - Channel Designation for General Purpose DMA & Trigger (Start) - page 2-28-4
- HDMAEN - Channel Designation for H-DMA - page 2-28-5
- MEMSEL - Access Cycle Designation in Memory - page 2-28-5
- RDNMI - NMI Flag By V-Blank & Version Number - page 2-28-6
- TIMEUP - IRQ Flag by H/V Count Timer - page 2-28-6
- HVBJOY - H/V Blank Flag & Standard Controller Enable Flag - page 2-28-7
- RDIO - Programmable I/O Port - page 2-28-7
- RDDIVL / RDDIVH - Quotient of Divide Result - page 2-28-8
- RDMPYL / RDMPYH - Product of Multiplication Result or Remainder of Divide Result - page 2-28-8
- STD CNTRRL1L / 1H / 2L/2H/3L/3H/4L/4H - Data for Standard Controller - page 2-28-9
Section 3 - Super NES Sound
Chapter 1. SNES Sound Source Outline - page 3-1-1
- System Outline - page 3-1-2
- Memory Mapping - page 3-1-3
- Signal Flow - page 3-1-4
Chapter 2. BRR (Bit Rate Reduction) - page 3-2-1
- Example Data when Filter = 0 - page 3-2-3
Chapter 3. I/O Ports - page 3-3-1
Chapter 4. Control Register - page 3-4-1
Chapter 5. Timers - page 3-5-1
- Timer Action - page 3-5-2
- Timer Related Registers - page 3-5-3
Chapter 6. DSP Interface Register - page 3-6-1
Chapter 7. Register Used - page 3-7-1
- Register Function - page 3-7-2
- ASDR Parameters - page 3-7-3
- GAIN - page 3-7-4
- Gain Parameters - page 3-7-5
- SRCN - page 3-7-6
- Complete Voice Registers - page 3-7-7
- EON - page 3-7-8
- ENDX - page 3-7-9
- Filter Setting Examples - page 3-7-10
- Sound Source Data (Source) Specifications - page 3-7-11
- Source Data - page 3-7-12
Chapter 8. CPU Organization - page 3-8-1
Chapter 9. Sound Programming Cautions - page 3-9-1
Section 4 - Super NES CPU Data (missing)
- Outline - page 4-1-1
- Explanation of CPU Terminal Functions - page 4-2-1
- Explanation of Functions - page 4-3-1
- Addressing Mode - page 4-4-1
- Command Set (Alphabetical Order) - page 4-5-1
- Command Set (Matrix Display) - page 4-6-1
- Cycles and Bytes of Addressing Modes - page 4-7-1
- Differences Among 65C816, 65C02, and 6502 - page 4-8-1
- Restrictions Upon Use & Application Information - page 4-9-1
- Details of Command Functions - page 4-10-1
- Description of Commands - page 4-11-1
- AC Characteristics - page 4-12-1
Tables of Appendix
Appendix A. PPU Registers - page A-1
- Object Data to be Stored - page A-2
- Object Data - page A-3
- Object Display - page A-4
- Object - page A-5
- Background Functions - page A-6
- Mosaic Screen - page A-7
- Address Increment Order - page A-8
- BG SC Data (Mode 0 ~ 6) - page A-10
- BG SC Data (Mode 7) - page A-11
- CHR Data Construction - page A-12
- Offset Change Mode - page A-13
- BG Screen - page A-14
- BG Screen (BG Mode 7) - page A-15
- Operation (Rotation/Enlargement/Reduction) - page A-16
- Operation CG-RAM - page A-17
- Window - page A-18
- BG & OBJ Priority - page A-19
- Screen - page A-20
- BG Screen - page A-21
- Figure A-1 SNES PPU Main/Sub Screen Window - page A-23
Appendix B. CPU Registers - page B-1
- H-DMA - page B-2
- Detect Beginning of V-Blank - page B-3
- Summary of Registers - page B-4
Appendix C SPC700 Commands - page C-1
- 8-bit Data Transmission Commands - page C-3
- Table C-7 8-bit Arithmetic Operation Commands - page C-5
- Table C-8 8-bit Logic Operation Commands - page C-6
- Addition, Subtraction, Shift, Rotation Commands - page C-7
Appendix D. Data Transfer Procedure - page D-1
- Data Transfer Instruction - page D-2
- Data Block Organization - page D-3
- Sound Boot Loader V1.1 - page D-4
Book II
- Table of Contents - page i
- List of Figures - page iii
- List of Tables - page vi
Section 1 - Super Accelerator (SA-1)
Chapter 1. Super Accelerator System Functions - page 1-1-1
- Arithmetic Hardware - page 1-1-2
- System Configuration - page 1-1-3
- Bus Image Diagram - page 1-1-4
Chapter 2. Configuration of SA-1 - page 1-2-1
- SA-1 CPU - page 1-2-2
- Memory Access - page 1-2-3
- BW-RAM Access - page 1-2-4
- SA-1 I-RAM Access - page 1-2-5
Chapter 3. Super Accelerator Memory Map - page 1-3-1
- Memory Map from SA-1 CPU Perspective - page 1-3-2
- Super MMC - page 1-3-3
- Protection of Backup Data - page 1-3-4
- Vectors and ROM-Registered Data - page 1-3-5
Chapter 4. SA-1 Internal Register Configuration - page 1-4-1
- SIE / SIC - page 1-4-2
- CRV / CNV / CIV - page 1-4-3
- SCNT - page 1-4-4
- CIE - page 1-4-5
- CIC - page 1-4-6
- SNV / SIV - page 1-4-7
- TMC / CTR - page 1-4-8
- HCNT / VCNT - page 1-4-9
- CXB - page 1-4-10
- DXB - page 1-4-11
- EXB - page 1-4-12
- FXB - page 1-4-13
- BMAPS - page 1-4-14
- BMAP - page 1-4-15
- SBWE / CDWE - page 1-4-16
- BWPA - page 1-4-17
- SIWP - page 1-4-18
- CIWP - page 1-4-19
- DCNT - page 1-4-20
- CDMA - page 1-4-21
- SDA / DDA - page 1-4-22
- DTC / BBF - page 1-4-23
- BRF - page 1-4-24
- MCNT - page 1-4-26
- MA / MB - page 1-4-27
- VBD - page 1-4-28
- VDA - page 1-4-29
- SFR - page 1-4-30
- CFR - page 1-4-30
- HCR / VCR - page 1-4-32
- MR - page 1-4-33
- OF / VDP - page 1-4-34
- VC - page 1-4-35
Chapter 5. Multi-Processor Processing - page 1-5-1
- MPU Handshakes - page 1-5-2
- Shared Memory - page 1-5-4
- SA-1 CPU Core - page 1-5-5
- Operation Modes - page 1-5-6
- Parallel Processing Mode - page 1-5-7
- Mixed Processing Mode - page 1-5-8
- Operating Modes and Processing Speeds - page 1-5-9
Chapter 6. Character Conversion - page 1-6-1
- Bitmap Access - page 1-6-3
- BW-RAM Data Expansion - page 1-6-5
- Character Conversion 1, Detailed Description - page 1-6-7
- Character Conversion 1 Programming Procedure - page 1-6-8
- Character Conversion 2, Detailed Description - page 1-6-10
- Character Conversion 2 Programming Procedure - page 1-6-11
Chapter 7. Arithmetic Function - page 1-7-1
- Multiplication - page 1-7-2
- Cumulative Sum - page 1-7-3
Chapter 8. Variable-Length Bit Processing - page 1-8-1
- Fixed Mode - page 1-8-2
- Auto-Increment Mode - page 1-8-3
- Variable-Length Data Processing Settings - page 1-8-4
Chapter 9. DMA - page 1-9-1
- Normal DMA Operation - page 1-9-2
- DMA Transmission Speed - page 1-9-4
Section 2 - Super FX
Chapter 1 Introduction to Super FX - page 2-1-1
- Special Conventions - page 2-1-2
- System Configurations - page 2-1-3
- System Operations - page 2-1-4
Chapter 2 GSU Functional Operation - page 2-2-1
- Registers - page 2-2-3
- Instruction Set - page 2-2-6
Chapter 3 Memory Mapping - page 2-3-1
- Super NES CPU Memory Map - page 2-3-2
- GSU Memory Mapping - page 2-3-3
- Super FX Memory Map - page 2-3-4
Chapter 4 GSU Internal Register Configuration - page 2-4-1
- Game Pak ROM Address Pointer (R14) - page 2-4-2
- Program Counter (R15) - page 2-4-3
- Status/Flag Register (SFR) - page 2-4-4
- Program Bank Register (PBR) - page 2-4-5
- Game Pak RAM Bank Register (RAMBR) - page 2-4-6
- Screen Base Register (SCBR) - page 2-4-7
- Screen Mode Register (SCMR) - page 2-4-8
- Color Register (COLR) - page 2-4-9
- Back-Up RAM Register (RAMBR) - page 2-4-10
- Config Register (CFGR) - page 2-4-11
Chapter 5 GSU Program Execution - page 2-5-1
- Starting GSU Program in Game Pak RAM - page 2-5-2
- Starting GSU Program in Cache RAM - page 2-5-3
- Memory Access from Super NES CPU During GSU Operation - page 2-5-4
Chapter 6 Instruction Execution - page 2-6-1
- Program Counter - page 2-6-3
- Register Prefixes - page 2-6-6
- LOOP - page 2-6-8
- Cache RAM - page 2-6-9
- Cache Operation - page 2-6-10
- Cache RAM Access from the Super NES - page 2-6-12
Chapter 7 Data Access - page 2-7-1
- GSU Program Running in Game Pak ROM - page 2-7-2
- Game Pak RAM Data - page 2-7-3
- Bulk Processing - page 2-7-4
Chapter 8 GSU Special Functions - page 2-8-1
- Plot Function and CMode - page 2-8-9
- Plot Data Address Calculation Methods - page 2-8-14
- Multiplication Instructions - page 2-8-16
Chapter 9 Description of Instructions - page 2-9-1
- ADC - page 2-9-3
- ADD - page 2-9-5
- ALT1 - page 2-9-7
- ALT2 - page 2-9-8
- ALT3 - page 2-9-9
- AND - page 2-9-11
- ASR - page 2-9-12
- BCC - page 2-9-14
- BCS - page 2-9-16
- BEQ - page 2-9-18
- BGE - page 2-9-20
- BIC - page 2-9-22
- BLT - page 2-9-24
- BMI - page 2-9-26
- BNE - page 2-9-28
- BPL - page 2-9-30
- BRA - page 2-9-32
- BVC - page 2-9-34
- BVS - page 2-9-36
- CACHE - page 2-9-38
- CMODE - page 2-9-39
- CMP - page 2-9-41
- COLOR - page 2-9-42
- DEC - page 2-9-43
- DIV2 - page 2-9-44
- FMULT - page 2-9-46
- FROM - page 2-9-48
- GETB - page 2-9-49
- GETBH - page 2-9-51
- GETBL - page 2-9-53
- GETBS - page 2-9-55
- GETC - page 2-9-57
- HIB - page 2-9-58
- IBT - page 2-9-60
- INC - page 2-9-61
- IWT - page 2-9-62
- JMP - page 2-9-63
- LDB - page 2-9-64
- LDW - page 2-9-66
- LEA - page 2-9-67
- LINK - page 2-9-68
- LJMP - page 2-9-69
- LM - page 2-9-70
- LMS - page 2-9-71
- LMULT - page 2-9-73
- LOB - page 2-9-75
- LOOP - page 2-9-77
- LSR - page 2-9-78
- MERGE - page 2-9-79
- MOVE - page 2-9-81
- MOVEB - page 2-9-87
- MOVES - page 2-9-89
- MOVEW - page 2-9-90
- MULT - page 2-9-93
- NOP - page 2-9-95
- NOT - page 2-9-96
- OR - page 2-9-97
- PLOT - page 2-9-100
- RAMB - page 2-9-101
- ROL - page 2-9-102
- ROMB - page 2-9-104
- ROR - page 2-9-105
- RPIX - page 2-9-107
- SBC - page 2-9-108
- SBK - page 2-9-109
- SEX - page 2-9-110
- SM - page 2-9-112
- SMS - page 2-9-113
- STB - page 2-9-115
- STOP - page 2-9-116
- STW - page 2-9-117
- SUB - page 2-9-118
- SWAP - page 2-9-120
- TO - page 2-9-121
- UMULT - page 2-9-122
Section 3 - DSP/DSP-1
Chapter 1 Introduction to DSP1 - page 3-1-1
- System Block Diagram (DSP1) - page 3-1-2
- DSP1 Operation - page 3-1-3
- Mode 20/DSP - page 3-1-4
- Mode 21/DSP - page 3-1-5
Chapter 2 Command Summary - page 3-2-1
Chapter 3 Parameter Data Type - page 3-3-1
Chapter 4 Use of DSP1 - page 3-4-1
- DSP1 Status Register - page 3-4-2
- Operation Summary - page 3-4-3
- Super NES CPU/DSP1 Operational Timing - page 3-4-4
Chapter 5 Description of DSP1 Commands - page 3-5-1
- Inverse Calculation (Floating Point) - page 3-5-2
- Trigonometric Calculation - page 3-5-3
- Vector Calculation - page 3-5-4
- Vector Size Comparison - page 3-5-6
- Vector Absolute Value Calculation - page 3-5-7
- Coordinate Calculation - page 3-5-8
- Three-Dimensional Coordinate Rotation - page 3-5-9
- Projection Calculation - page 3-5-12
- Raster Data Calculation - page 3-5-15
- Object Projection Calculation - page 3-5-18
- Coordinate Calculation of a Selected Point on the Screen - page 3-5-20
- Attitude Control - page 3-5-22
- Convert From Global to Object Coordinates - page 3-5-25
- Conversion From Object to Global Coordinates - page 3-5-17
- Calculation of Inner Product with Forward Attitude and a Vector - page 3-5-29
- New Angle Calculation - page 3-5-31
Chapter 6 Math Functions and Equations - page 3-6-1
Section 4 - Accessories
Chapter 1. The Super NES Super Scope System - page 4-1-1
- Super NES Super Scope Sight Adjustment - page 4-1-2
- Basic Super NES Super Scope Specifications - page 4-1-3
- Super NES Program Address - page 4-1-4
Chapter 2. Principles of the Super NES Super Scope - page 4-2-1
- Super NES Super Scope Programming - page 4-2-3
- The Super NES Horizontal/Vertical Counter - page 4-2-4
Chapter 3. Super NES Super Scope Functional Operation - page 4-3-1
- Super NES Super Scope Flow Diagram - page 4-3-2
- Infa-red Data Transmission Format - page 4-3-3
- Communication Codes - page 4-3-4
- Raster Signal Transmission Timing - page 4-3-5
Chapter 4. Super NES Super Scope Receiver Functions - page 4-4-1
- Operations Flow Diagram - page 4-4-2
- Super NES Super Scope Receiver Interface - page 4-4-3
- Code Pulse Detection - page 4-4-4
- Raster Pulse Detection - page 4-4-5
- Functional Description - page 4-4-6
- Trigger Mode (Single Shot) - page 4-4-7
- Trigger Mode (Multiple Shots) - page 4-4-8
- Null Bit / Pause Bit - page 4-4-9
- Cursor + Trigger Cycle - page 4-4-10
- Trigger (Multiple Shots) - page 4-4-11
Chapter 5. Graphics - page 4-5-1
Chapter 6. Super NES Mouse Specifications - page 4-6-1
- Super NES Mouse Data Flow - page 4-6-2
- Speed Switching - page 4-6-4
- Data - page 4-6-5
- X, Y Absolute Displacement (SD16-SD31) - page 4-6-6
- Super NES Mouse Specifications - page 4-6-7
Chapter 7. Using the Standard BIOS - page 4-7-1
- Mouse Serial Data Read Routine - page 4-7-2
- Super NES Mouse Speed Switching Routine - page 4-7-4
- Using the Program - page 4-7-5
- Speed Selection and Cursor Movement - page 4-7-6
- Registers - page 4-7-7
Chapter 8 Programming Cautions - page 4-8-1
- Caution #5 - page 4-8-2
Chapter 9 MultiPlayer 5 Specifications - page 4-9-1
- Hardware Connections - page 4-9-2
- Modes of Operation - page 4-9-3
- Programming Cautions for Compatible Software - page 4-9-4
- Reading Data - page 4-9-5
- Peripheral Device Connections - page 4-9-7
- Identifying Devices Connected to MultiPlayer 5 - page 4-9-9
- MultiPlayer 5 Schematic Diagram - page 4-9-10
- Reading Controller Data - page 4-9-11
- Controller I/O Ports - page 4-9-12
Chapter 10 MultiPlayer 5 Supplied BIOS - page 4-10-1
- Supplied BIOS Execution - page 4-10-2
- Supplied BIOS Output Register - page 4-10-3
- Supplied BIOS Cautions - page 4-10-4
- MultiPlayer 5 Supplied BIOS Program Listings - page 4-10-6
- MultiPlayer Development Assembly - page 4-10-14
Supplemental Information
- Super NES Parts List - page 1
- Game Content Guidelines - page 3 (missing)
- Guidelines Concerning Commercialism and Promotion of Licensee (missing)
- Products or Services in Nintendo Licensed Games - page 5 (missing)
- Super NES Video Timing Information - page 10 (missing)