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SEP: Difference between revisions

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(RTI also sets m and x flags)
 
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'''SEP''' (Set Status Bits) is a [[65c816]] instruction that sets bits in the [[status register]] that correspond to set bits in the operand.
'''SEP''' (Set Status Bits) is a [[65c816]] instruction that sets bits in the [[status register]] that correspond to set bits in the operand.
SEP appears to be the only way to set the m and x flags other than [[PLP]] and [[RTI]].


=== See Also ===
=== See Also ===
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[[Category:Two-byte Instructions]]
[[Category:Two-byte Instructions]]
[[Category:Three-cycle Instructions]]
[[Category:Three-cycle Instructions]]
[[Category:Single Admode Mnemonics]]

Latest revision as of 16:51, 14 December 2023

Basic Info
Addressing Mode Opcode Length Speed
Immediate E2 2 bytes 3 cycles
Flags Affected
N V M X D I Z C
emulation mode . .
native mode

SEP (Set Status Bits) is a 65c816 instruction that sets bits in the status register that correspond to set bits in the operand.

SEP appears to be the only way to set the m and x flags other than PLP and RTI.

See Also

External Links