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Timing Control Unit
From SnesLab
The Timing Control Unit (TCU) is part of the 65c816. It contains a counter that is reset at each instruction fetch and advances during each machine cycle. Together with the instruction register, it helps the processor perform register transfers.
List of instructions with cycle penalties:
- ADC
- AND
- ASL
- BCC
- BCS
- BEQ
- BIT
- BMI
- BNE
- BPL
- BRA
- BRK
- BVC
- BVS
- CMP
- COP
- CPX
- CPY
- DEC
- EOR
- INC
- LDA
- LDX
- LDY
- LSR
- ORA
- PEI
- PHA
- PHX
- PHY
- PLA
- PLX
- PLY
- ROL
- ROR
- RTI
- SBC
- STA
- STX
- STY
- STZ
- TRB
- TSB
- and most SPC700 branching commands
List of instructions without cycle penalties:
- BRL
- CLC
- CLD
- CLI
- CLV
- DEX
- DEY
- INX
- INY
- JMP / JML
- JSL
- JSR
- MVN
- MVP
- NOP
- PEA
- PER
- PHB
- PHD
- PHK
- PHP
- PLB
- PLD
- PLP
- REP
- RTL
- RTS
- SEC
- SED
- SEI
- SEP
- STP
- TAX
- TAY
- TCD
- TCS
- TDC
- TSC
- TSX
- TXA
- TXS
- TXY
- TYA
- TYX
- WAI
- WDM
- XBA
- XCE
- All non-branching SPC700 instructions
- BRA (SPC700)
- JMP (SPC700)
Reference
- section 2.2 of 65c816 datasheet: https://www.westerndesigncenter.com/wdc/documentation/w65c816s.pdf