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Pixel Clock

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The Pixel Clock signal is generated by the PPU by dividing the Master Clock frequency by 4. On NTSC, the pixel clock is 5.37 MHz. On PAL, 5.32 MHz. [1]

According to the ares source code, the PPU usually emits one dot every 4 CPU clock cycles (typo for master cycles?), but some long dots take more cycles. [2]

See Also

References

  1. https://problemkaputt.de/fullsnes.htm#snestimingoscillators
  2. ares/sfc/ppu/counter/inline.hpp:61