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LSR: Difference between revisions

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!colspan="9"|Flags Affected
!colspan="9"|Flags Affected
|+
|+
|N
|[[N Flag|N]]
|V
|[[V Flag|V]]
|M
|[[M Flag|M]]
|X
|[[X Flag|X]]
|D
|[[D Flag|D]]
|I
|[[I Flag|I]]
|Z
|[[Z Flag|Z]]
|C
|[[C Flag|C]]
|+
|+
|0
|0

Revision as of 03:07, 27 November 2023

Basic Info
Addressing Mode Opcode Length Speed
Accumulator 4A 1 byte 2 cycles
Absolute 4E 3 bytes 6 cycles*
Direct Page 46 2 bytes 5 cycles*
absolute indexed X 5E 3 bytes 7 cycles*
direct page indexed X 56 2 bytes 6 cycles*
Flags Affected
N V M X D I Z C
0 . . . . .

LSR (Logical Shift Right) is a 65x instruction that shifts a value one bit to the right (division by two). The most significant bit becomes a zero. The least significant bit is shifted into the carry flag.

Cycle Penalties

See Also

External Links