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Index Register Select: Difference between revisions
From SnesLab
(bit 5) |
(added instructions that can affect it) |
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It is not possible to control the width of the two index registers individually. | It is not possible to control the width of the two index registers individually. | ||
It can be affected by: | |||
* [[REP]] | |||
* [[SEP]] | |||
* [[PLP]] | |||
* [[RTI]] | |||
=== See Also === | === See Also === |
Revision as of 23:33, 6 July 2024
Index Register Select is a flag in the processor status register (bit 5). It indicates how wide the index registers are.
When clear, both index registers are 16 bits wide. When set, both index registers are 8 bits wide.
It is not possible to control the width of the two index registers individually.
It can be affected by: