IBT: Difference between revisions

Latest revision as of 02:24, 16 July 2024


Basic Info
Addressing Mode	Opcode	Length	ROM Speed	RAM Speed	Cache Speed
Immediate	Anpp	2 bytes	6 cycles	6 cycles	2 cycles


Flags Affected
B	ALT1	ALT2	O/V	S	CY	Z
0	0	0	.	.	.	.

IBT (Immediate Byte Transfer) is a Super FX instruction that loads an immediate byte into the low byte of a specified general register. The register's upper eight bits will be sign-extended (copied) from bit 7, effectively loading a signed 8-bit value.

The ALT0 state is restored.

Syntax

IBT Rn, #pp

where pp may be from -128 to 127. Any of the 16 general registers can be specified.

Example

IBT R₈, #4    ; 0004h -> R₈
IBT R₈, #-128 ; ff80h -> R₈
IBT R₈, #0A4h ; ffa4h -> R₈

Trivia

The word "integer" is misspelled in the official manual page for IBT.

External Links

Official Nintendo documentation on IBT: 9.41 on Page 2-9-60 of Book II

@@ Line 26: / Line 26: @@
 |[[Sign Flag|S]]
 |[[CY]]
-|Z
+|[[Zero Flag|Z]]
 |+
 |0
@@ Line 37: / Line 37: @@
 |}
-'''IBT''' (Immediate Byte Data?) is a [[Super FX]] instruction that loads an immediate byte into the low byte of a specified register.  The register's upper eight bits will be sign-extended (copied) from bit 7, effectively loading a signed 8-bit value.
+'''IBT''' (Immediate Byte Transfer) is a [[Super FX]] instruction that loads an immediate byte into the low byte of a specified general register.  The register's upper eight bits will be sign-extended (copied) from bit 7, effectively loading a signed 8-bit value.
+The [[ALT0]] state is restored.
+==== Syntax ====
+<pre>
+IBT Rn, #pp
+</pre>
+where pp may be from -128 to 127.  Any of the 16 general registers can be specified.
+==== Example ====
+ IBT R<sub>8</sub>, #4    ; 0004h -> R<sub>8</sub>
+ IBT R<sub>8</sub>, #-128 ; ff80h -> R<sub>8</sub>
+ IBT R<sub>8</sub>, #0A4h ; ffa4h -> R<sub>8</sub>
+==== Trivia ====
+The word "integer" is misspelled in the official manual page for IBT.
+[[File:ibt.png]]
 === See Also ===