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OR1 (SPC700): Difference between revisions
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|'''Speed''' | |'''Speed''' | ||
|+ | |+ | ||
| | |[[Absolute Boolean Bit]] | ||
|0A | |0A | ||
|3 bytes | |3 bytes | ||
|5 cycles | |5 cycles | ||
|+ | |+ | ||
| | |[[Absolute Boolean Bit]] | ||
|2A | |2A | ||
|3 bytes | |3 bytes | ||
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{| class="wikitable" style="float:right;clear:right;width:30%" | {| class="wikitable" style="float:right;clear:right;width:30%" | ||
!colspan="8"|Flags | !colspan="8"|Flags Affected | ||
|+ | |+ | ||
|N | |[[Negative Flag|N]] | ||
|V | |[[Overflow Flag|V]] | ||
|P | |[[Direct Page Flag|P]] | ||
|B | |[[Break Flag|B]] | ||
|H | |[[Half-Carry Flag|H]] | ||
|I | |[[Interrupt Enable Flag|I]] | ||
|Z | |[[Zero Flag|Z]] | ||
|C | |[[Carry Flag|C]] | ||
|+ | |+ | ||
|. | |. | ||
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| | |C | ||
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'''OR1''' is an [[SPC700]] instruction that performs a logical or between a memory bit and the [[carry flag]], then stores the disjunction in the carry flag. | '''OR1''' is an [[SPC700]] instruction that performs a logical or between a memory bit and the [[carry flag]], then stores the disjunction in the carry flag. The low 13 bits of the operand byte specify an absolute address. The high 3 bits of the operand byte specify which bit at that absolute address. | ||
The [[bit reversal]] operator may be prefixed to the memory bit address, in which case opcode 2A is assembled. | |||
==== Syntax ==== | |||
<pre> | |||
OR1 C, mem. bit | |||
OR1 C, /mem. bit | |||
</pre> | |||
=== See Also === | === See Also === | ||
* [[OR (SPC700)]] | |||
* [[AND1]] | * [[AND1]] | ||
* [[EOR1]] | * [[EOR1]] | ||
* [[MOV1]] | |||
* [[NOT1]] | |||
=== External Links === | === External Links === | ||
* Official Super Nintendo development manual on OR1: [https://archive.org/details/SNESDevManual/book1/page/n234 Appendix C-9 of Book I] | * Official Super Nintendo development manual on OR1: [https://archive.org/details/SNESDevManual/book1/page/n234 Appendix C-9 of Book I] | ||
* subparagraph 8.2.3.3 of [https://archive.org/details/SNESDevManual/book1/page/n186 page 3-8-8], lbid. | |||
* anomie: https://github.com/yupferris/TasmShiz/blob/master/spc700.txt#L531 | |||
[[Category:ASM]] | [[Category:ASM]] | ||
[[Category:SPC700]] | [[Category:SPC700]] | ||
[[Category:Bit Operation Commands]] | [[Category:Bit Operation Commands]] | ||
[[Category:Three-byte Instructions]] | |||
Latest revision as of 14:08, 30 July 2024
| Basic Info | |||||||
|---|---|---|---|---|---|---|---|
| Addressing Mode | Opcode | Length | Speed | ||||
| Absolute Boolean Bit | 0A | 3 bytes | 5 cycles | ||||
| Absolute Boolean Bit | 2A | 3 bytes | 5 cycles | ||||
| Flags Affected | |||||||
|---|---|---|---|---|---|---|---|
| N | V | P | B | H | I | Z | C |
| . | . | . | . | . | . | . | C |
OR1 is an SPC700 instruction that performs a logical or between a memory bit and the carry flag, then stores the disjunction in the carry flag. The low 13 bits of the operand byte specify an absolute address. The high 3 bits of the operand byte specify which bit at that absolute address.
The bit reversal operator may be prefixed to the memory bit address, in which case opcode 2A is assembled.
Syntax
OR1 C, mem. bit OR1 C, /mem. bit
See Also
External Links
- Official Super Nintendo development manual on OR1: Appendix C-9 of Book I
- subparagraph 8.2.3.3 of page 3-8-8, lbid.
- anomie: https://github.com/yupferris/TasmShiz/blob/master/spc700.txt#L531