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Program Counter Relative Addressing: Difference between revisions
From SnesLab
(all of these are on the 65c816) |
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* [[Program Counter Relative Long Addressing]] | * [[Program Counter Relative Long Addressing]] | ||
=== | === References === | ||
* [[Eyes & Lichty]] | * [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/399 page 399] | ||
* section 3.5.21 of 65c816 datasheet, https://westerndesigncenter.com/wdc/documentation/w65c816s.pdf | * section 3.5.21 of 65c816 datasheet, https://westerndesigncenter.com/wdc/documentation/w65c816s.pdf | ||
* Clark, Bruce. http://www.6502.org/tutorials/65c816opcodes.html#5.18 | * Clark, Bruce. http://www.6502.org/tutorials/65c816opcodes.html#5.18 | ||
Revision as of 19:34, 8 August 2024
Program Counter Relative Addressing is supported by nine instructions on the 65c816:
- BCC (opcode 90)
- BCS (opcode B0)
- BEQ (opcode F0)
- BMI (opcode 30)
- BNE (opcode D0)
- BPL (opcode 10)
- BRA (opcode 80)
- BVC (opcode 50)
- BVS (opcode 70)
All of which are two bytes long.
The effective address is generated by sign-extending the 8-bit operand to 16 bits and then adding it to the program counter. The program bank register remains the same.
Syntax
BRA label
See Also
References
- Eyes & Lichty, page 399
- section 3.5.21 of 65c816 datasheet, https://westerndesigncenter.com/wdc/documentation/w65c816s.pdf
- Clark, Bruce. http://www.6502.org/tutorials/65c816opcodes.html#5.18