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LSR (SPC700): Difference between revisions

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|'''Speed'''
|'''Speed'''
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|[[Accumulator Addressing | Accumulator]]
|5C
|5C
|1 byte
|1 byte
|2 cycles
|2 cycles
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|[[Direct Page Addressing | Direct Page]]
|4B
|4B
|2 bytes
|2 bytes
|4 cycles
|4 cycles
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|[[Direct Page Indexed by X]]
|5B
|5B
|2 bytes
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|5 cycles
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|[[Absolute Addressing | Absolute]]
|4C
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|3 bytes
|3 bytes
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{| class="wikitable" style="float:right;clear:right;width:30%"
{| class="wikitable" style="float:right;clear:right;width:30%"
!colspan="8"|Flags Clobbered
!colspan="8"|Flags Affected
|+
|[[Negative Flag|N]]
|[[Overflow Flag|V]]
|[[Direct Page Flag|P]]
|[[Break Flag|B]]
|[[Half-Carry Flag|H]]
|[[Interrupt Enable Flag|I]]
|[[Zero Flag|Z]]
|[[Carry Flag|C]]
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|+
|N
|N
|V
|P
|B
|H
|I
|Z
|C
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'''LSR''' (Logical Shift Right) is an [[SPC700]] instruction that shifts its operand one bit to the right.  The least significant bit is shifted into the [[carry flag]].  A zero is shifted into the most significant bit.
'''LSR''' (Logical Shift Right) is an [[SPC700]] instruction that shifts all 8 bits of its operand one bit to the right, dividing it by two.  The least significant bit is shifted into the [[carry flag]].  A zero is shifted into the most significant bit.
 
The official manual has the bit shift operators for LSR pointing the wrong way.
 
==== Syntax ====
<pre>
LSR A
LSR dp
LSR dp+X
LSR !abs
</pre>
 
[[File:lsr_spc.png]]
 
LSR is a fast alternative to [[DIV]] when dividing by a power of two.


=== See Also ===
=== See Also ===
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=== External Links ===
=== External Links ===
* Official Super Nintendo development manual on LSR: [https://archive.org/details/SNESDevManual/book1/page/n232 Appendix C-7 of Book I]
* Official Super Nintendo development manual on LSR: [https://archive.org/details/SNESDevManual/book1/page/n232 Appendix C-7 of Book I]
* anomie: https://github.com/yupferris/TasmShiz/blob/master/spc700.txt#L457


[[Category:ASM]]
[[Category:ASM]]
[[Category:SPC700]]
[[Category:SPC700]]
[[Category:Shift Rotation Commands]]
[[Category:Shift Rotation Commands]]

Latest revision as of 00:04, 15 August 2024

Basic Info
Addressing Mode Opcode Length Speed
Accumulator 5C 1 byte 2 cycles
Direct Page 4B 2 bytes 4 cycles
Direct Page Indexed by X 5B 2 bytes 5 cycles
Absolute 4C 3 bytes 5 cycles
Flags Affected
N V P B H I Z C
N . . . . . Z C

LSR (Logical Shift Right) is an SPC700 instruction that shifts all 8 bits of its operand one bit to the right, dividing it by two. The least significant bit is shifted into the carry flag. A zero is shifted into the most significant bit.

The official manual has the bit shift operators for LSR pointing the wrong way.

Syntax

LSR A
LSR dp
LSR dp+X
LSR !abs

lsr spc.png

LSR is a fast alternative to DIV when dividing by a power of two.

See Also

External Links