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CLD: Difference between revisions
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!colspan="8"|Basic Info | !colspan="8"|Basic Info | ||
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|'''Speed''' | |'''Speed''' | ||
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| | |[[Implied]] (type 2) | ||
|D8 | |D8 | ||
|1 byte | |1 byte | ||
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!colspan="9"|Flags | !colspan="9"|Flags Affected | ||
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|N | |[[Negative Flag|N]] | ||
|V | |[[Overflow Flag|V]] | ||
|M | |[[M Flag|M]] | ||
|X | |[[X Flag|X]] | ||
|D | |[[Decimal Flag|D]] | ||
|I | |[[I Flag|I]] | ||
|Z | |[[Zero Flag|Z]] | ||
|C | |[[Carry Flag|C]] | ||
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|. | |. | ||
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'''CLD''' is a 65x instruction that clears the [[decimal mode flag]], switching the processor back into binary mode so [[ADC]] and [[SBC]] will operate normally. Hexadecimal digits A through F may appear in sums/differences. | |||
No other flags are affected. | |||
==== Syntax ==== | |||
<pre> | |||
CLD | |||
</pre> | |||
[[BRK]] handlers do not need CLD because BRK also clears the decimal flag. | |||
To clear more than one flag at the same time, use [[REP]]. | |||
=== See Also === | === See Also === | ||
* [[SED]] | * [[SED]] | ||
* [[ | * [[CLC]] | ||
* [[CLV]] | |||
* [[Binary Coded Decimal]] | |||
=== External Links === | === External Links === | ||
* [[Eyes & Lichty]] page on CLD: https://archive.org/details/ | * [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/442 page 442] on CLD | ||
* [[ | * [[Labiak]], [https://archive.org/details/Programming_the_65816/page/n141 page 131] on CLD | ||
* 3.3.2 on [[MCS6500 Manual]], [https://archive.org/details/mos_microcomputers_programming_manual/page/n42 page 27] on CLD | |||
* [[Carr]], [https://archive.org/details/6502UsersManual/page/n267 page 254] on CLD | |||
* [[Leventhal]], [https://archive.org/details/6502-assembly-language-programming/page/n102 page 3-53] on CLD | |||
* snes9x implementation of CLD: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L1434 | |||
* Clark, Bruce. http://www.6502.org/tutorials/65c816opcodes.html#6.4.1 | |||
[[Category:ASM]] | [[Category:ASM]] | ||
[[Category:Inherited from 6502]] | [[Category:Inherited from 6502]] | ||
[[Category:One-byte Instructions]] | |||
[[Category:Implied Instructions]] | |||
[[Category:Two-cycle Instructions]] | |||
Latest revision as of 17:32, 20 September 2024
| Basic Info | |||||||
|---|---|---|---|---|---|---|---|
| Addressing Mode | Opcode | Length | Speed | ||||
| Implied (type 2) | D8 | 1 byte | 2 cycles | ||||
| Flags Affected | ||||||||
|---|---|---|---|---|---|---|---|---|
| N | V | M | X | D | I | Z | C | |
| . | . | . | . | 0 | . | . | . | |
CLD is a 65x instruction that clears the decimal mode flag, switching the processor back into binary mode so ADC and SBC will operate normally. Hexadecimal digits A through F may appear in sums/differences.
No other flags are affected.
Syntax
CLD
BRK handlers do not need CLD because BRK also clears the decimal flag.
To clear more than one flag at the same time, use REP.
See Also
External Links
- Eyes & Lichty, page 442 on CLD
- Labiak, page 131 on CLD
- 3.3.2 on MCS6500 Manual, page 27 on CLD
- Carr, page 254 on CLD
- Leventhal, page 3-53 on CLD
- snes9x implementation of CLD: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L1434
- Clark, Bruce. http://www.6502.org/tutorials/65c816opcodes.html#6.4.1