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Official Documentation Quick Links: Difference between revisions
From SnesLab
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* [https://archive.org/details/SNESDevManual/book1/page/n17 Chapter 2. Super NES Software Submission Requirements] | * [https://archive.org/details/SNESDevManual/book1/page/n17 Chapter 2. Super NES Software Submission Requirements] | ||
[https://archive.org/details/SNESDevManual/book1/page/n57 Chapter 1. Introduction] | * [https://archive.org/details/SNESDevManual/book1/page/n57 Chapter 1. Introduction] | ||
[https://archive.org/details/SNESDevManual/book1/page/n59 Chapter 2. Object (OBJ)] | * [https://archive.org/details/SNESDevManual/book1/page/n59 Chapter 2. Object (OBJ)] | ||
[https://archive.org/details/SNESDevManual/book1/page/n61 Chapter 3. Background (BG)] | * [https://archive.org/details/SNESDevManual/book1/page/n61 Chapter 3. Background (BG)] | ||
[https://archive.org/details/SNESDevManual/book1/page/n63 Chapter 4. Mosaic] | * [https://archive.org/details/SNESDevManual/book1/page/n63 Chapter 4. Mosaic] | ||
[https://archive.org/details/SNESDevManual/book1/page/n65 Chapter 5. Rotation/Enlargement/Reduction] | * [https://archive.org/details/SNESDevManual/book1/page/n65 Chapter 5. Rotation/Enlargement/Reduction] | ||
[https://archive.org/details/SNESDevManual/book1/page/n67 Chapter 6. Window (Window Mask)] | * [https://archive.org/details/SNESDevManual/book1/page/n67 Chapter 6. Window (Window Mask)] | ||
[https://archive.org/details/SNESDevManual/book1/page/n67 Chapter 7. Main/Sub Screen] | * [https://archive.org/details/SNESDevManual/book1/page/n67 Chapter 7. Main/Sub Screen] | ||
[https://archive.org/details/SNESDevManual/book1/page/n73 Chapter 8. CG Direct Select] | * [https://archive.org/details/SNESDevManual/book1/page/n73 Chapter 8. CG Direct Select] | ||
[https://archive.org/details/SNESDevManual/book1/page/n73 Chapter 9. H-Pseudo 512] | * [https://archive.org/details/SNESDevManual/book1/page/n73 Chapter 9. H-Pseudo 512] | ||
[https://archive.org/details/SNESDevManual/book1/page/n75 Chapter 10. Complementary Multiplication (Signed Multiplication)] | * [https://archive.org/details/SNESDevManual/book1/page/n75 Chapter 10. Complementary Multiplication (Signed Multiplication)] | ||
[https://archive.org/details/SNESDevManual/book1/page/n75 Chapter 11. H/V Counter Latch] | * [https://archive.org/details/SNESDevManual/book1/page/n75 Chapter 11. H/V Counter Latch] | ||
[https://archive.org/details/SNESDevManual/book1/page/n77 Chapter 12. Offset Change] | * [https://archive.org/details/SNESDevManual/book1/page/n77 Chapter 12. Offset Change] | ||
[https://archive.org/details/SNESDevManual/book1/page/n77 Chapter 13. Standard Controller] | * [https://archive.org/details/SNESDevManual/book1/page/n77 Chapter 13. Standard Controller] | ||
[https://archive.org/details/SNESDevManual/book1/page/n79 Chapter 14. Programmable I/O Port] | * [https://archive.org/details/SNESDevManual/book1/page/n79 Chapter 14. Programmable I/O Port] | ||
[https://archive.org/details/SNESDevManual/book1/page/n81 Chapter 15. Absolute Multiplication/Division] | * [https://archive.org/details/SNESDevManual/book1/page/n81 Chapter 15. Absolute Multiplication/Division] | ||
[https://archive.org/details/SNESDevManual/book1/page/n81 Chapter 16. H/V Count Timer] | * [https://archive.org/details/SNESDevManual/book1/page/n81 Chapter 16. H/V Count Timer] | ||
[https://archive.org/details/SNESDevManual/book1/page/n83 Chapter 17. Direct Memory Access (DMA)] | * [https://archive.org/details/SNESDevManual/book1/page/n83 Chapter 17. Direct Memory Access (DMA)] | ||
[https://archive.org/details/SNESDevManual/book1/page/n87 Chapter 18. Interlace] | * [https://archive.org/details/SNESDevManual/book1/page/n87 Chapter 18. Interlace] | ||
[https://archive.org/details/SNESDevManual/book1/page/n89 Chapter 19. H-512 Mode (BG Mode 5 & 6)] | * [https://archive.org/details/SNESDevManual/book1/page/n89 Chapter 19. H-512 Mode (BG Mode 5 & 6)] | ||
[https://archive.org/details/SNESDevManual/book1/page/n89 Chapter 20. OBJ 33's Lines Over & Priority Order] | * [https://archive.org/details/SNESDevManual/book1/page/n89 Chapter 20. OBJ 33's Lines Over & Priority Order] | ||
[https://archive.org/details/SNESDevManual/book1/page/n91 Chapter 21. CPU Clock and Memory Mapping] | * [https://archive.org/details/SNESDevManual/book1/page/n91 Chapter 21. CPU Clock and Memory Mapping] | ||
[https://archive.org/details/SNESDevManual/book1/page/n97 Chapter 22. Super NES Functional Operation] | * [https://archive.org/details/SNESDevManual/book1/page/n97 Chapter 22. Super NES Functional Operation] | ||
[https://archive.org/details/SNESDevManual/book1/page/n99 Chapter 23. System Flowchart] | * [https://archive.org/details/SNESDevManual/book1/page/n99 Chapter 23. System Flowchart] | ||
[https://archive.org/details/SNESDevManual/book1/page/n103 Chapter 24. Programming Cautions] | * [https://archive.org/details/SNESDevManual/book1/page/n103 Chapter 24. Programming Cautions] | ||
[https://archive.org/details/SNESDevManual/book1/page/n111 Chapter 25. Documented Problems] | * [https://archive.org/details/SNESDevManual/book1/page/n111 Chapter 25. Documented Problems] | ||
[https://archive.org/details/SNESDevManual/book1/page/n113 Chapter 26. Register Clear (Initial Settings)] | * [https://archive.org/details/SNESDevManual/book1/page/n113 Chapter 26. Register Clear (Initial Settings)] | ||
[https://archive.org/details/SNESDevManual/book1/page/n113 Chapter 27. PPU Registers] | * [https://archive.org/details/SNESDevManual/book1/page/n113 Chapter 27. PPU Registers] | ||
[https://archive.org/details/SNESDevManual/book1/page/n139 Chapter 28. CPU Registers] | * [https://archive.org/details/SNESDevManual/book1/page/n139 Chapter 28. CPU Registers] | ||
[https://archive.org/details/SNESDevManual/book1/page/n151 Chapter 1. SNES Sound Source Outline] | * [https://archive.org/details/SNESDevManual/book1/page/n151 Chapter 1. SNES Sound Source Outline] | ||
[https://archive.org/details/SNESDevManual/book1/page/n155 Chapter 2. BRR (Bit Rate Reduction)] | * [https://archive.org/details/SNESDevManual/book1/page/n155 Chapter 2. BRR (Bit Rate Reduction)] | ||
Revision as of 23:37, 13 May 2023
- Chapter 1. Introduction
- Chapter 2. Object (OBJ)
- Chapter 3. Background (BG)
- Chapter 4. Mosaic
- Chapter 5. Rotation/Enlargement/Reduction
- Chapter 6. Window (Window Mask)
- Chapter 7. Main/Sub Screen
- Chapter 8. CG Direct Select
- Chapter 9. H-Pseudo 512
- Chapter 10. Complementary Multiplication (Signed Multiplication)
- Chapter 11. H/V Counter Latch
- Chapter 12. Offset Change
- Chapter 13. Standard Controller
- Chapter 14. Programmable I/O Port
- Chapter 15. Absolute Multiplication/Division
- Chapter 16. H/V Count Timer
- Chapter 17. Direct Memory Access (DMA)
- Chapter 18. Interlace
- Chapter 19. H-512 Mode (BG Mode 5 & 6)
- Chapter 20. OBJ 33's Lines Over & Priority Order
- Chapter 21. CPU Clock and Memory Mapping
- Chapter 22. Super NES Functional Operation
- Chapter 23. System Flowchart
- Chapter 24. Programming Cautions
- Chapter 25. Documented Problems
- Chapter 26. Register Clear (Initial Settings)
- Chapter 27. PPU Registers
- Chapter 28. CPU Registers