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Official Documentation Quick Links: Difference between revisions

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(more Book I links)
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* [https://archive.org/details/SNESDevManual/book1/page/n13 Chapter 1.  NOA Licensed Software Approval Process]
* [https://archive.org/details/SNESDevManual/book1/page/n13 Chapter 1.  NOA Licensed Software Approval Process]
* [https://archive.org/details/SNESDevManual/book1/page/n17 Chapter 2. Super NES Software Submission Requirements]
* [https://archive.org/details/SNESDevManual/book1/page/n17 Chapter 2. Super NES Software Submission Requirements]


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* [https://archive.org/details/SNESDevManual/book1/page/n151 Chapter 1. SNES Sound Source Outline]
* [https://archive.org/details/SNESDevManual/book1/page/n151 Chapter 1. SNES Sound Source Outline]
* [https://archive.org/details/SNESDevManual/book1/page/n155 Chapter 2. BRR (Bit Rate Reduction)]
* [https://archive.org/details/SNESDevManual/book1/page/n155 Chapter 2. BRR (Bit Rate Reduction)]
* [https://archive.org/details/SNESDevManual/book1/page/n159 Chapter 3. I/O Ports]
* [https://archive.org/details/SNESDevManual/book1/page/n161 Chapter 4. Control Register]
* [https://archive.org/details/SNESDevManual/book1/page/n163 Chapter 5. Timers]
* [https://archive.org/details/SNESDevManual/book1/page/n165 Chapter 6. DSP Interface Register]
* [https://archive.org/details/SNESDevManual/book1/page/n167 Chapter 7. Register Used]
* [https://archive.org/details/SNESDevManual/book1/page/n179 Chapter 8. CPU Organization]
* [https://archive.org/details/SNESDevManual/book1/page/n187 Chapter 9. Sound Programming Cautions]
* [https://archive.org/details/SNESDevManual/book1/page/n217 Appendix B. CPU Registers]
* [https://archive.org/details/SNESDevManual/book1/page/n225 Appendix C SPC700 Commands]
* [https://archive.org/details/SNESDevManual/book1/page/n235 Appendix D. Data Transfer Procedure]

Revision as of 23:42, 13 May 2023