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Book I

• Table of Contents - page i
• List of Figures - page v
• List of Tables - page ix
• Preface - page 1
• Confidentiality Agreement - page 2

Section 1 - Approval Process

• Chapter 1. NOA Licensed Software Approval Process - page 1-1-1
• Chapter 2. Super NES Software Submission Requirements - page 1-2-1

Section 2 - Super NES Software

• Chapter 1. Introduction - page 2-1-1
• Chapter 2. Object (OBJ) - page 2-2-1
• Chapter 3. Background (BG) - page 2-3-1
• Chapter 4. Mosaic - page 2-4-1
• Chapter 5. Rotation/Enlargement/Reduction - page 2-5-1
• Chapter 6. Window (Window Mask) - page 2-6-1
• Chapter 7. Main/Sub Screen - page 2-7-1
• Chapter 8. CG Direct Select - page 2-8-1
• Chapter 9. H-Pseudo 512 - page 2-9-1
• Chapter 10. Complementary Multiplication (Signed Multiplication) - page 2-10-1
• Chapter 11. H/V Counter Latch - page 2-11-1
• Chapter 12. Offset Change - page 2-12-1
• Chapter 13. Standard Controller - page 2-13-1
• Chapter 14. Programmable I/O Port - page 2-14-1
• Chapter 15. Absolute Multiplication/Division - page 2-15-1
• Chapter 16. H/V Count Timer - page 2-16-1
• Chapter 17. Direct Memory Access (DMA) - page 2-17-1
• Chapter 18. Interlace - page 2-18-1
• Chapter 19. H-512 Mode (BG Mode 5 & 6) - page 2-19-1
• Chapter 20. OBJ 33's Lines Over & Priority Order - page 2-20-1
• Chapter 21. CPU Clock and Memory Mapping - page 2-21-1
• Chapter 22. Super NES Functional Operation - page 2-22-1
• Chapter 23. System Flowchart - page 2-23-1
• Chapter 24. Programming Cautions - page 2-24-1
• Chapter 25. Documented Problems - page 2-25-1
• Chapter 26. Register Clear (Initial Settings) - page 2-26-1
• Chapter 27. PPU Registers - page 2-27-1
  • INIDISP
  • OBJSEL
  • OAMADDL / OAMADDH
  • OAM DATA
  • BG MODE aka BGMODE
  • MOSAIC
  • BG1SC / BG2SC / BG3SC / BG4SC
  • BG1NBA / BG34NBA
  • BG1H0FS / BG1V0FS
  • BG2H0FS / BG2V0FS / BG3H0FS / BG3V0FS / BG40FS / BG4V0FS
  • VMAINC
  • VMADDL / VMADDH
  • VMDATAL / VMDATAH
  • M7SEL
  • M7A / M7B / M7C / M7D / M7X / M7Y
  • CGADD / CGDATA
  • W12SEL / W34SEL / WOBJSEL
  • WH0 / WH1 / WH2 / WH3
  • WBGLOG / WOBJLOG
  • TM
  • TS
  • TMW
  • TSW
  • CGSWEL
  • CGADSUB
  • COLDATA
  • SETINI
  • MPYL / MPYM / MPYH
  • SLHV
  • OAMDATA
  • VMDATAL / VMDATAH
  • CGDATA
  • OPHCT / OPVCT
  • STAT77 / STAT78
  • APUIO0 / APUIO1 / APUIO2 / APUIO3
  • WMDATA
  • WMADDL / WMADDM / WMADDH

• Chapter 28. CPU Registers - page 2-28-1
  • NMITIMEN
  • WRIO
  • WRMPYA / WRMPYB
  • WRDIVL / WRDIVH / WRDIVB
  • HTIMEL / HTIMEH
  • VTIMEL / VTIMEH
  • MDMAEN
  • HDMAEN
  • MEMSEL
  • RDNMI
  • TIMEUP
  • HVBJOY
  • RDIO
  • RDDIVL / RDDIVH
  • RDMPYL / RDMPYH
  • STD CNTRRL1L / 1H / 2L/2H/3L/3H/4L/4H

Section 3 - Super NES Sound

• Chapter 1. SNES Sound Source Outline - page 3-1-1
• Chapter 2. BRR (Bit Rate Reduction) - page 3-2-1
• Chapter 3. I/O Ports - page 3-3-1
• Chapter 4. Control Register - page 3-4-1
• Chapter 5. Timers - page 3-5-1
• Chapter 6. DSP Interface Register - page 3-6-1
• Chapter 7. Register Used - page 3-7-1
• Chapter 8. CPU Organization - page 3-8-1
• Chapter 9. Sound Programming Cautions - page 3-9-1

Tables of Appendix

• Appendix A. PPU Registers - page A-1
• Appendix B. CPU Registers - page B-1
• Appendix C SPC700 Commands - page C-1
• Appendix D. Data Transfer Procedure - page D-1

Book II

• Cover Page

• Table of Contents - page i

• List of Figures - page iii

• List of Tables - page vi

Section 1 - Super Accelerator (SA-1)

• Chapter 1. Super Accelerator System Functions - page 1-1-1
• Chapter 2. Configuration of SA-1 - page 1-2-1
• Chapter 3. Super Accelerator Memory Map - page 1-3-1
• Chapter 4. SA-1 Internal Register Configuration - page 1-4-1
• Chapter 5. Multi-Processor Processing - page 1-5-1
• Chapter 6. Character Conversion - page 1-6-1
• Chapter 7. Arithmetic Function - page 1-7-1
• Chapter 8. Variable-Length Bit Processing - page 1-8-1
• Chapter 9. DMA - page 1-9-1

Section 2 - Super FX

• Chapter 1 Introduction to Super FX - page 2-1-1
• Chapter 2 GSU Functional Operation - page 2-2-1
• Chapter 3 Memory Mapping - page 2-3-1
• Chapter 4 GSU Internal Register Configuration - page 2-4-1
• Chapter 5 GSU Program Execution - page 2-5-1
• Chapter 6 Instruction Execution - page 2-6-1
• Chapter 7 Data Access - page 2-7-1
• Chapter 8 GSU Special Functions - page 2-8-1
• Chapter 9 Description of Instructions - page 2-9-1
  • ADC
  • ADD
  • ALT1
  • ALT2
  • ALT3
  • AND
  • ASR
  • BCC
  • BCS
  • BEQ
  • BGE
  • BIC
  • BLT
  • BMI
  • BNE
  • BPL
  • BRA
  • BVC
  • BVS
  • CACHE
  • CMODE
  • CMP
  • COLOR
  • DEC
  • DIV2
  • FMULT
  • FROM
  • GETB
  • GETBH
  • GETBL
  • GETBS
  • GETC
  • HIB
  • IBT
  • INC
  • IWT
  • JMP
  • LDB
  • LDW
  • LEA
  • LINK
  • LJMP
  • LM
  • LMS
  • LMULT
  • LOB
  • LOOP
  • LSR
  • MERGE
  • MOVE
  • MOVEB
  • MOVES
  • MOVEW
  • MULT
  • NOP
  • NOT
  • OR
  • PLOT
  • RAMB
  • ROL
  • ROMB
  • ROR
  • RPIX
  • SBC
  • SBK
  • SEX
  • SM
  • SMS
  • STB
  • STOP
  • STW
  • SUB
  • SWAP
  • TO
  • UMULT

Section 3 - DSP/DSP-1

• Chapter 1 Introduction to DSP1 - page 3-1-1
• Chapter 2 Command Summary - page 3-2-1
• Chapter 3 Parameter Data Type - page 3-3-1
• Chapter 4 Use of DSP1 - page 3-4-1
• Chapter 5 Description of DSP1 Commands - page 3-5-1
• Chapter 6 Math Functions and Equations - page 3-6-1

Section 4 - Accessories

• Chapter 1. The Super NES Super Scope System - page 4-1-1
• Chapter 2. Principles of the Super NES Super Scope - page 4-2-1
• Chapter 3. Super NES Super Scope Functional Operation - page 4-3-1
• Chapter 4. Super NES Super Scope Receiver Functions - page 4-4-1
• Chapter 5. Graphics - page 4-5-1
• Chapter 6. Super NES Mouse Specifications - page 4-6-1
• Chapter 7. Using the Standard BIOS - page 4-7-1
• Chapter 8 Programming Cautions - page 4-8-1
• Chapter 9 MultiPlayer 5 Specifications - page 4-9-1
• Chapter 10 MultiPlayer 5 Supplied BIOS - page 4-10-1
• Chapter 1. Super NES Parts List - page 1
• Index for Book I
• Index for Book II