We've just updated MediaWiki and its underlying software. If anything doesn't look or work quite right, please mention it to us. --RanAS

Write-Twice Register: Difference between revisions

From SnesLab
Jump to: navigation, search
(linkify CPU data bus)
(buffer category)
Line 9: Line 9:


[[Category:SNES Hardware]]
[[Category:SNES Hardware]]
[[Category:Buffers]]

Revision as of 01:00, 17 July 2023

A write-twice register is a 16-bit register that is mapped to only 8-bits in an address space. The motivation behind write-twice registers is that they prevent glitches caused by software accidentally only updating half of a 16-bit register. This is accomplished via an additional, hidden 8-bit buffer.

  • On the first write, the 8-bit value from the CPU Data Bus is written to the hidden buffer, but the contents of the 16-bit register are not updated yet.
  • On the second write, both the new 8-bit value from the CPU's data bus and the buffered 8-bit value both overwrite the old contents of the 16-bit register simultaneously.

References