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DEC (SPC700): Difference between revisions
From SnesLab
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(implied addressing) |
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|5 cycles | |5 cycles | ||
|+ | |+ | ||
| | |[[Implied]] (type 1) | ||
|1D | |1D | ||
|1 byte | |1 byte | ||
|2 cycles | |2 cycles | ||
|+ | |+ | ||
| | |[[Implied]] (type 1) | ||
|DC | |DC | ||
|1 byte | |1 byte | ||
Revision as of 20:10, 23 July 2023
| Basic Info | |||||||
|---|---|---|---|---|---|---|---|
| Addressing Mode | Opcode | Length | Speed | ||||
| Accumulator | 9C | 1 byte | 2 cycles | ||||
| Direct Page | 8B | 2 byte | 4 cycles | ||||
| Direct Page Indexed by X | 9B | 2 byte | 5 cycles | ||||
| Absolute | 8C | 3 bytes | 5 cycles | ||||
| Implied (type 1) | 1D | 1 byte | 2 cycles | ||||
| Implied (type 1) | DC | 1 byte | 2 cycles | ||||
| Flags Clobbered | |||||||
|---|---|---|---|---|---|---|---|
| N | V | P | B | H | I | Z | C |
| . | . | . | . | . | . | ||
DEC is an SPC700 instruction that decrements its operand.
See Also
External Links
- Official Super Nintendo development manual on DEC: Appendix C-7 of Book I