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ARAM Write Enable Flag: Difference between revisions
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The '''ARAM Write Enable Flag''' is bit 1 of the [[S-SMP]]'s TEST register (00F0h) | The '''ARAM Write Enable Flag''' is bit 1 of the [[S-SMP]]'s TEST register (00F0h): | ||
When set, the S-SMP and S-DSP can both read and write ARAM. | * When set, the S-SMP and [[S-DSP]] can both read and write to [[ARAM]]. | ||
When clear, they can only read ARAM. | * When clear, they can only read ARAM. | ||
=== Reference === | === Reference === | ||
Latest revision as of 01:02, 14 August 2024
The ARAM Write Enable Flag is bit 1 of the S-SMP's TEST register (00F0h):