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AND1 (SPC700): Difference between revisions

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The [[bit reversal]] operator may be prefixed to the memory bit address, in which case opcode 6A is assembled.
The [[bit reversal]] operator may be prefixed to the memory bit address, in which case opcode 6A is assembled.
==== Syntax ====
<pre>
AND1 C, mem. bit
AND1 C, /mem. bit
</pre>


=== See Also ===
=== See Also ===
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* Official Nintendo documentation on AND1: Table C-18 in [https://archive.org/details/SNESDevManual/book1/page/n234 Appendix C-9 of Book I]
* Official Nintendo documentation on AND1: Table C-18 in [https://archive.org/details/SNESDevManual/book1/page/n234 Appendix C-9 of Book I]
* subparagraph 8.2.3.3 of [https://archive.org/details/SNESDevManual/book1/page/n186 page 3-8-8], lbid.
* subparagraph 8.2.3.3 of [https://archive.org/details/SNESDevManual/book1/page/n186 page 3-8-8], lbid.
* anomie: https://github.com/yupferris/TasmShiz/blob/master/spc700.txt#L332


[[Category:ASM]]
[[Category:ASM]]

Latest revision as of 13:52, 30 July 2024

Basic Info
Addressing Mode Opcode Length Speed
Absolute Boolean Bit 4A 3 bytes 4 cycles
Absolute Boolean Bit 6A 3 bytes 4 cycles
Flags Affected
N V P B H I Z C
. . . . . . . C

AND1 is an SPC700 instruction that performs a logical AND between a memory bit and the carry flag, then stores the conjunction in the carry flag. The low 13 bits of the operand specify an absolute address. The high 3 bits of the operand specify which bit at that absolute address.

The bit reversal operator may be prefixed to the memory bit address, in which case opcode 6A is assembled.

Syntax

AND1 C, mem. bit
AND1 C, /mem. bit

See Also

External Links