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STOP (Super FX): Difference between revisions
From SnesLab
(type 2 implied) |
(→External Links: bsnes imp) |
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|[[Sign Flag|S]] | |[[Sign Flag|S]] | ||
|[[CY]] | |[[CY]] | ||
|Z | |[[Zero Flag|Z]] | ||
|+ | |+ | ||
|0 | |0 | ||
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'''STOP''' is a [[Super FX]] instruction that clears the [[Go flag]], stopping the processor. An [[IRQ]] is generated. | '''STOP''' is a [[Super FX]] instruction that clears the [[Go flag]], stopping the processor. An [[IRQ]] is generated. | ||
The [[ALT0]] state is restored. | |||
==== Syntax ==== | |||
<pre> | |||
STOP | |||
</pre> | |||
=== See Also === | === See Also === | ||
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=== External Links === | === External Links === | ||
* Official Super Nintendo development manual on STOP: 9.84 on [https://archive.org/details/SNESDevManual/book2/page/n272 page 2-9-116 of Book II] | * Official Super Nintendo development manual on STOP: 9.84 on [https://archive.org/details/SNESDevManual/book2/page/n272 page 2-9-116 of Book II] | ||
* 6.8.4 GSU Exclusive Operation in Cache RAM on page 2-6-12 of Book II | |||
* bsnes implementation: https://github.com/bsnes-emu/bsnes/blob/master/bsnes/sfc/coprocessor/superfx/core.cpp#L1 | |||
[[Category:ASM]] | [[Category:ASM]] | ||
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[[Category:GSU Control Instructions]] | [[Category:GSU Control Instructions]] | ||
[[Category:One-byte Instructions]] | [[Category:One-byte Instructions]] | ||
[[Category:Single Admode Mnemonics]] | |||
Latest revision as of 09:50, 22 July 2024
| Basic Info | |||||||
|---|---|---|---|---|---|---|---|
| Addressing Mode | Opcode | Length | ROM Speed | RAM Speed | Cache Speed | ||
| Implied (type 2) | 00 | 1 byte | 3 cycles | 3 cycles | 1 cycle | ||
| Flags Affected | ||||||||
|---|---|---|---|---|---|---|---|---|
| B | ALT1 | ALT2 | O/V | S | CY | Z | ||
| 0 | 0 | 0 | . | . | . | . | ||
STOP is a Super FX instruction that clears the Go flag, stopping the processor. An IRQ is generated.
The ALT0 state is restored.
Syntax
STOP
See Also
External Links
- Official Super Nintendo development manual on STOP: 9.84 on page 2-9-116 of Book II
- 6.8.4 GSU Exclusive Operation in Cache RAM on page 2-6-12 of Book II
- bsnes implementation: https://github.com/bsnes-emu/bsnes/blob/master/bsnes/sfc/coprocessor/superfx/core.cpp#L1