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Interrupt Disable Flag: Difference between revisions

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The '''Interrupt Disable Flag''' (I) exists on the [[65c816]] as bit 2 of the [[status register]].
The '''Interrupt Disable Flag''' (I) is bit 2 of the [[65c816]]'s [[status register]].


[[SEI]] sets it and [[CLI]] clears it.
[[SEI]] sets it and [[CLI]] clears it.  ([[SEP]] and [[REP]] can as well.)  [[BRK]] and [[COP]] set it too.


This flag is automatically set whenever the processor begins servicing an interrupt.
This flag is automatically set whenever the processor begins servicing an interrupt.
[[BRK]] ignores its previous state.
There are no BIS or BIC instructions that examine this flag (though there is an unrelated [[BIC (Super FX)]] instruction).


=== See Also ===
=== See Also ===
* [[REP]]
* [[SEP]]
* [[Interrupt Enable Flag]]
* [[Interrupt Enable Flag]]
* [[IRQ]]
* [[IRQ]]
* [[NMI]]
* [[NMI]]
=== Reference ===
* Pickens, John.  NMOS 6502 Opcodes.  http://www.6502.org/tutorials/6502opcodes.html#IFLAG


[[Category:ASM]]
[[Category:ASM]]
[[Category:Flags]]
[[Category:Flags]]
[[Category:Inherited from 6502]]
[[Category:Inherited from 6502]]
[[Category:Mode Select Flags]]

Latest revision as of 14:56, 16 August 2024

The Interrupt Disable Flag (I) is bit 2 of the 65c816's status register.

SEI sets it and CLI clears it. (SEP and REP can as well.) BRK and COP set it too.

This flag is automatically set whenever the processor begins servicing an interrupt.

BRK ignores its previous state.

There are no BIS or BIC instructions that examine this flag (though there is an unrelated BIC (Super FX) instruction).

See Also

Reference