SEP: Difference between revisions

Latest revision as of 20:37, 17 August 2024


Basic Info
Addressing Mode	Opcode	Length	Speed
Immediate	E2	2 bytes	3 cycles


Flags Affected
	N	V	M	X	D	I	Z	C
emulation mode	N	V	.	.	D	I	Z	C
native mode	N	V	M	X	D	I	Z	C

SEP (Set Status Bits) is a 65c816 instruction that sets bits in the status register that correspond to set bits in the operand.

SEP is the only way to set the m and x flags directly without disturbing the stack (but PLP and RTI may set them too.)^[1] But, SEP can't modify those two flags in emulation mode because they are being forced to be set.

Syntax

SEP #%nvmxdizc

If you only want to set one flag, SED, SEI, or SEC are smaller/faster than SEP. Early 65c816 chips had a timing problem with SEP and REP which required a NOP to be inserted after them, or to stretch the clock.^[5]

References

Eyes & Lichty, page 502 on SEP
Labiak, page 183 on SEP
snes9x implementation of SEP: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L3203
undisbeliever on SEP: https://undisbeliever.net/snesdev/65816-opcodes.html#sep-set-status-bits
http://forum.6502.org/viewtopic.php?f=4&t=5196

@@ Line 1: / Line 1: @@
-'''SEP''' is a [[65c816]] instruction that sets bits in the [[status register]] that correspond to set bits in the operand.
+{| class="wikitable" style="float:right;clear:right;width:40%"
-{| class="wikitable" style="float:right;clear:right;width:30%"
 !colspan="8"|Basic Info
 |+
@@ Line 9: / Line 7: @@
 |'''Speed'''
 |+
-|immediate
+|[[Immediate]]
 |E2
 |2 bytes
@@ Line 15: / Line 13: @@
 |}
-{| class="wikitable" style="float:right;clear:right;width:30%"
+{| class="wikitable" style="float:right;clear:right;width:40%"
-!colspan="9"|Flags Clobbered
+!colspan="9"|Flags Affected
+|+
+|
+|[[Negative Flag|N]]
+|[[Overflow Flag|V]]
+|[[M Flag|M]]
+|[[X Flag|X]]
+|[[Decimal Flag|D]]
+|[[I Flag|I]]
+|[[Zero Flag|Z]]
+|[[Carry Flag|C]]
+|+
+| [[emulation mode]]
+|N
+|V
+|.
+|.
+|D
+|I
+|Z
+|C
 |+
+| [[native mode]]
 |N
 |V
@@ Line 26: / Line 45: @@
 |Z
 |C
-|+
-|
-|
-|
-|
-|
-|
-|
-|
 |}
+'''SEP''' (Set Status Bits) is a [[65c816]] instruction that sets bits in the [[status register]] that correspond to set bits in the operand.
+SEP is the only way to set the m and x flags directly without disturbing the [[stack]] (but [[PLP]] and [[RTI]] may set them too.)<sup>[1]</sup>  But, SEP can't modify those two flags in [[emulation mode]] because they are being forced to be set.
+==== Syntax ====
+<pre>
+SEP #%nvmxdizc
+</pre>
+If you only want to set one flag,  [[SED]], [[SEI]], or [[SEC]] are smaller/faster than SEP.  Early 65c816 chips had a timing problem with SEP and [[REP]] which required a [[NOP]] to be inserted after them, or to stretch the clock.<sup>[5]</sup>
 === See Also ===
-* [[REP]]
+* [[TSB]]
+* [[Derailment]]
-=== External Links ===
+=== References ===
-* [[Eyes & Lichty]] page on SEP: https://archive.org/details/0893037893ProgrammingThe65816/page/n528
+# [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/502 page 502] on SEP
+# [[Labiak]], [https://archive.org/details/Programming_the_65816/page/n193 page 183] on SEP
+# snes9x implementation of SEP: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L3203
+# undisbeliever on SEP: https://undisbeliever.net/snesdev/65816-opcodes.html#sep-set-status-bits
+# http://forum.6502.org/viewtopic.php?f=4&t=5196
 [[Category:ASM]]
 [[Category:65c816 additions]]
+[[Category:Two-byte Instructions]]
+[[Category:Three-cycle Instructions]]
+[[Category:Single Admode Mnemonics]]