LSR: Difference between revisions

Latest revision as of 17:45, 23 August 2024


Basic Info
Addressing Mode	Opcode	Length	Speed
Accumulator	4A	1 byte	2 cycles
Absolute	4E	3 bytes	6 cycles*
Direct Page	46	2 bytes	5 cycles*
Absolute Indexed by X	5E	3 bytes	7 cycles*
Direct Page Indexed by X	56	2 bytes	6 cycles*


Flags Affected
N	V	M	X	D	I	Z	C
0	.	.	.	.	.	Z	C

LSR (Logical Shift Right) is a 65x instruction that shifts every bit of a value one bit to the right (division by two). The most significant bit and negative flag are cleared. The least significant bit is shifted into the carry flag. The previous value of the carry flag is lost (unlike with ROR).

The size of the accumulator determines how many bits are shifted (8 or 16) not including the clearing zero and carry flag.

Syntax

LSR
LSR A
LSR addr
LSR dp
LSR addr, X
LSR dp, X

Cycle Penalties

Except in accumulator addressing, LSR takes an extra two cycles when the accumulator is 16 bits wide
In direct page addressing modes, LSR takes another extra cycle if the low byte of the direct page register is nonzero.

External Links

Eyes & Lichty, page 465 on LSR
lbid page 191, before & after diagram of LSR
Labiak, page 152 on LSR
10.1 on MCS6500 Manual, page 148 on LSR
Carr, page 265 on LSR
Leventhal, page 3-76 on LSR
snes9x implementation of LSR: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L862
undisbeliever on LSR: https://undisbeliever.net/snesdev/65816-opcodes.html#lsr-logical-shift-right
Pickens, John. http://www.6502.org/tutorials/6502opcodes.html#LSR
Clark, Bruce. http://www.6502.org/tutorials/65c816opcodes.html#6.1.3

@@ Line 1: / Line 1: @@
-'''LSR''' (Logical Shift Right) is a 65x instruction that shifts a value one bit to the right (division by two).  The most significant bit becomes a zero.  The least significant bit is shifted into the [[carry flag]].
+{| class="wikitable" style="float:right;clear:right;width:40%"
-{| class="wikitable" style="float:right;clear:right;width:30%"
 !colspan="8"|Basic Info
 |+
@@ Line 9: / Line 7: @@
 |'''Speed'''
 |+
-|accumulator
+|[[Accumulator Addressing|Accumulator]]
 |4A
 |1 byte
 |2 cycles
 |+
-|absolute
+|[[Absolute]]
 |4E
 |3 bytes
-|6 cycles
+|6 cycles*
 |+
-|direct page
+|[[Direct Page Addressing|Direct Page]]
 |46
 |2 bytes
-|5 cycles
+|5 cycles*
 |+
-|absolute indexed X
+|[[Absolute Indexed by X]]
 |5E
 |3 bytes
-|7 cycles
+|7 cycles*
 |+
-|direct page indexed X
+|[[Direct Page Indexed by X]]
 |56
 |2 bytes
-|6 cycles
+|6 cycles*
 |}
-{| class="wikitable" style="width:30%"
+{| class="wikitable" style="float:right;clear:right;width:30%"
-!colspan="9"|Flags Clobbered
+!colspan="9"|Flags Affected
 |+
-|N
+|[[N Flag|N]]
-|V
+|[[V Flag|V]]
-|M
+|[[M Flag|M]]
-|X
+|[[X Flag|X]]
-|D
+|[[D Flag|D]]
-|I
+|[[I Flag|I]]
-|Z
+|[[Z Flag|Z]]
-|C
+|[[C Flag|C]]
 |+
 |0
@@ Line 53: / Line 51: @@
 |.
 |.
-|
+|Z
-|
+|C
 |}
+'''LSR''' (Logical Shift Right) is a 65x instruction that shifts every bit of a value one bit to the right (division by two).  The most significant bit and [[negative flag]] are cleared.  The least significant bit is shifted into the [[carry flag]].  The previous value of the carry flag is lost (unlike with [[ROR]]).
+The size of the accumulator determines how many bits are shifted (8 or 16) not including the clearing zero and carry flag.
+==== Syntax ====
+<pre>
+LSR
+LSR A
+LSR addr
+LSR dp
+LSR addr, X
+LSR dp, X
+</pre>
+==== Cycle Penalties ====
+* Except in [[accumulator addressing]], LSR takes an extra two cycles when the accumulator is 16 bits wide
+* In [[direct page addressing]] modes, LSR takes another extra cycle if the low byte of the [[direct page register]] is nonzero.
+[[File:816_lsr.png]]
+=== See Also ===
+* [[ASL]]
+* [[LSR (SPC700)]]
+* [[LSR (Super FX)]]
+* [[DIV2]]
 === External Links ===
-* [[Eyes & Lichty]] page on LSR: https://archive.org/details/0893037893ProgrammingThe65816/page/n491
+* [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/465 page 465] on LSR
-* [[Labiak]] page on LSR: https://archive.org/details/Programming_the_65816/page/n162
+* lbid [https://archive.org/details/0893037893ProgrammingThe65816/page/191 page 191], before & after diagram of LSR
-* [[MCS6500 Manual]] page on LSR: https://archive.org/details/mos_microcomputers_programming_manual/page/n169
+* [[Labiak]], [https://archive.org/details/Programming_the_65816/page/n162 page 152] on LSR
-* [[Carr]] page on LSR: https://archive.org/details/6502UsersManual/page/n278
+* 10.1 on [[MCS6500 Manual]], [https://archive.org/details/mos_microcomputers_programming_manual/page/n169 page 148] on LSR
-* [[Leventhal]] page on LSR: https://archive.org/details/6502-assembly-language-programming/page/n125
+* [[Carr]], [https://archive.org/details/6502UsersManual/page/n278 page 265] on LSR
+* [[Leventhal]], [https://archive.org/details/6502-assembly-language-programming/page/n125 page 3-76] on LSR
+* snes9x implementation of LSR: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L862
+* undisbeliever on LSR: https://undisbeliever.net/snesdev/65816-opcodes.html#lsr-logical-shift-right
+* Pickens, John. http://www.6502.org/tutorials/6502opcodes.html#LSR
+* Clark, Bruce. http://www.6502.org/tutorials/65c816opcodes.html#6.1.3
 [[Category:ASM]]