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Bank Address Register: Difference between revisions
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The '''Bank Address Register''' is Nintendo's name for the 8-bit register that fills in the most significant bits of a 24-bit address memory access by the [[5A22]]. It keeps track of what bank the CPU is configured to use. | ''Note: this page is likely inaccurate/confusing;'' | ||
The '''Bank Address Register''' (also known as the '''bank byte''') is Nintendo's name for the 8-bit register that fills in the most significant bits of a 24-bit address memory access by the [[5A22]]. It keeps track of what [[bank]] the CPU is configured to use. It is cleared to zero on reset.<sup>[2]</sup> | |||
WDC calls this register the '''Data Bank Register''' (DBR). | |||
[[PLB]], [[MVN]], and [[MVP]] modify this register. [[PHB]] pushes it onto the [[stack]]. [[TSB]] does not transfer the [[stack pointer]] to the DBR despite appearing like a transfer mnemonic. | |||
=== See Also === | |||
* [[Program Bank Register]] | |||
* [[Address Bus A]] | |||
=== References === | === References === | ||
# Figure 2-21-2 on [https://archive.org/details/SNESDevManual/book1/page/n94 page 2-21-3 of Book I] of the official Super Nintendo development manual | |||
# section 2.5 on page 6 of 65c816 datasheet, https://westerndesigncenter.com/wdc/documentation/w65c816s.pdf | |||
# [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/53 page 53] | |||
# lbid, [https://archive.org/details/0893037893ProgrammingThe65816/page/55 page 55] | |||
# lbid, [https://archive.org/details/0893037893ProgrammingThe65816/page/114 page 114] | |||
[[Category:Registers]] | [[Category:Registers]] | ||
[[Category:ASM]] | [[Category:ASM]] | ||
[[Category:Bank Registers]] | |||
Latest revision as of 01:02, 17 August 2024
Note: this page is likely inaccurate/confusing;
The Bank Address Register (also known as the bank byte) is Nintendo's name for the 8-bit register that fills in the most significant bits of a 24-bit address memory access by the 5A22. It keeps track of what bank the CPU is configured to use. It is cleared to zero on reset.[2]
WDC calls this register the Data Bank Register (DBR).
PLB, MVN, and MVP modify this register. PHB pushes it onto the stack. TSB does not transfer the stack pointer to the DBR despite appearing like a transfer mnemonic.
See Also
References
- Figure 2-21-2 on page 2-21-3 of Book I of the official Super Nintendo development manual
- section 2.5 on page 6 of 65c816 datasheet, https://westerndesigncenter.com/wdc/documentation/w65c816s.pdf
- Eyes & Lichty, page 53
- lbid, page 55
- lbid, page 114