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AND1 (SPC700): Difference between revisions
From SnesLab
(→External Links: section 8.2.3.3) |
(13-bit -> Absolute Boolean Bit) |
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| Line 7: | Line 7: | ||
|'''Speed''' | |'''Speed''' | ||
|+ | |+ | ||
|[[ | |[[Absolute Boolean Bit]] | ||
|4A | |4A | ||
|3 bytes | |3 bytes | ||
|4 cycles | |4 cycles | ||
|+ | |+ | ||
|[[ | |[[Absolute Boolean Bit]] | ||
|6A | |6A | ||
|3 bytes | |3 bytes | ||
Revision as of 07:33, 18 December 2023
| Basic Info | |||||||
|---|---|---|---|---|---|---|---|
| Addressing Mode | Opcode | Length | Speed | ||||
| Absolute Boolean Bit | 4A | 3 bytes | 4 cycles | ||||
| Absolute Boolean Bit | 6A | 3 bytes | 4 cycles | ||||
| Flags Affected | |||||||
|---|---|---|---|---|---|---|---|
| N | V | P | B | H | I | Z | C |
| . | . | . | . | . | . | . | |
AND1 is an SPC700 instruction that performs a logical AND between a memory bit and the carry flag, then stores the conjunction in the carry flag. The low 13 bits of the operand specify an absolute address. The high 3 bits of the operand specify which bit at that absolute address.
See Also
External Links
- Official Nintendo documentation on AND1: Table C-18 in Appendix C-9 of Book I
- section 8.2.3.3 of page 3-8-8, lbid.