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IBT: Difference between revisions
From SnesLab
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==== Syntax ==== | ==== Syntax ==== | ||
<pre> | <pre> | ||
IBT Rn, #pp | IBT Rn, #pp | ||
</pre> | </pre> | ||
where pp may be from -128 to 127. | |||
=== See Also === | === See Also === | ||
Revision as of 07:50, 9 July 2024
| Basic Info | |||||||
|---|---|---|---|---|---|---|---|
| Addressing Mode | Opcode | Length | ROM Speed | RAM Speed | Cache Speed | ||
| Immediate | Anpp | 2 bytes | 6 cycles | 6 cycles | 2 cycles | ||
| Flags Affected | ||||||||
|---|---|---|---|---|---|---|---|---|
| B | ALT1 | ALT2 | O/V | S | CY | Z | ||
| 0 | 0 | 0 | . | . | . | . | ||
IBT (Immediate Byte Transfer) is a Super FX instruction that loads an immediate byte into the low byte of a specified register. The register's upper eight bits will be sign-extended (copied) from bit 7, effectively loading a signed 8-bit value.
Syntax
IBT Rn, #pp
where pp may be from -128 to 127.
See Also
External Links
- Official Nintendo documentation on IBT: 9.41 on Page 2-9-60 of Book II