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Processor Status Register: Difference between revisions
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=== Reference === | === Reference === | ||
# Table 18.2 [[Eyes & Lichty]], page 422: https://archive.org/details/0893037893ProgrammingThe65816/page/ | # Table 18.2 [[Eyes & Lichty]], page 422: https://archive.org/details/0893037893ProgrammingThe65816/page/422 | ||
# Figure 17.3, Lbid, page 377: https://archive.org/details/0893037893ProgrammingThe65816/page/n403 | # Figure 17.3, Lbid, page 377: https://archive.org/details/0893037893ProgrammingThe65816/page/n403 | ||
# page 262, https://archive.org/details/0893037893ProgrammingThe65816/page/n288 | # page 262, https://archive.org/details/0893037893ProgrammingThe65816/page/n288 | ||
Revision as of 11:35, 17 July 2024
The Processor Status Register (P) is on the 65c816 and contains several flags:
- n
- v
- m
- x
- d
- i
- z
- c
It can be pulled from the stack via PLP and RTI.
There are nine instructions that directly modify these flags, including:[3]
The only transfer instructions that do not modify these flags are TCS and TXS.
See Also
Reference
- Table 18.2 Eyes & Lichty, page 422: https://archive.org/details/0893037893ProgrammingThe65816/page/422
- Figure 17.3, Lbid, page 377: https://archive.org/details/0893037893ProgrammingThe65816/page/n403
- page 262, https://archive.org/details/0893037893ProgrammingThe65816/page/n288