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FLG: Difference between revisions
From SnesLab
(ECEN) |
(RES) |
||
| Line 3: | Line 3: | ||
Bit 5 is ECEN. | Bit 5 is ECEN. | ||
Bit 6 is MUTE. | Bit 6 is MUTE. | ||
Bit 7 is RES. | |||
The low 5 bits are [[NCK]]. | The low 5 bits are [[NCK]]. | ||
Latest revision as of 12:22, 17 July 2024
FLG is an 8-bit DSPRAM register located at 6Ch.
Bit 5 is ECEN. Bit 6 is MUTE. Bit 7 is RES.
The low 5 bits are NCK.
Reference
- page 3-7-8 of Book I of the official Super Nintendo development manual