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Pixel Clock: Difference between revisions
From SnesLab
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The '''Pixel Clock''' signal is generated by the [[PPU]] by dividing the [[Master Clock]] frequency by 4. On NTSC, the pixel clock is 5.37 MHz. On PAL, 5.32 MHz. <sup>[1]</sup> | The '''Pixel Clock''' signal is generated by the [[PPU]] by dividing the [[Master Clock]] frequency by 4. On NTSC, the pixel clock is 5.37 MHz. On PAL, 5.32 MHz. <sup>[1]</sup> | ||
According to the ares source code, the PPU usually emits one dot every 4 [[Machine Cycle|CPU clock cycles]] (typo for master cycles?), but some long dots take more cycles. <sup>[2]</sup> | |||
=== See Also === | === See Also === | ||
Latest revision as of 21:19, 18 August 2024
The Pixel Clock signal is generated by the PPU by dividing the Master Clock frequency by 4. On NTSC, the pixel clock is 5.37 MHz. On PAL, 5.32 MHz. [1]
According to the ares source code, the PPU usually emits one dot every 4 CPU clock cycles (typo for master cycles?), but some long dots take more cycles. [2]
See Also
References
- https://problemkaputt.de/fullsnes.htm#snestimingoscillators
- ares/sfc/ppu/counter/inline.hpp:61