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Pixel Clock: Difference between revisions
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The '''Pixel Clock''' signal is generated by the [[PPU]] by dividing the [[Master Clock]] frequency by 4. On NTSC, the pixel clock is 5.37 MHz. On PAL, 5.32 MHz. | The '''Pixel Clock''' signal is generated by the [[PPU]] by dividing the [[Master Clock]] frequency by 4. On NTSC, the pixel clock is 5.37 MHz. On PAL, 5.32 MHz. [1] | ||
The PPU usually emits one dot every 4 CPU clock cycles, but some long dots take more cycles. [2] | |||
=== References === | === References === | ||
* https://problemkaputt.de/fullsnes.htm#snestimingoscillators | * [1] https://problemkaputt.de/fullsnes.htm#snestimingoscillators | ||
* [2] ares/sfc/ppu/counter/inline.hpp:61 | |||
[[Category:SNES Hardware]] | [[Category:SNES Hardware]] | ||
Revision as of 03:21, 2 June 2023
The Pixel Clock signal is generated by the PPU by dividing the Master Clock frequency by 4. On NTSC, the pixel clock is 5.37 MHz. On PAL, 5.32 MHz. [1]
The PPU usually emits one dot every 4 CPU clock cycles, but some long dots take more cycles. [2]
References
- [1] https://problemkaputt.de/fullsnes.htm#snestimingoscillators
- [2] ares/sfc/ppu/counter/inline.hpp:61