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Master Clock: Difference between revisions
From SnesLab
(linkify jwdonal schematic) |
(see also the other two oscs) |
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[[File:master clock schematic.png|thumb|The master clock (X1) is in region A4 of the [[jwdonal schematic]]]] | [[File:master clock schematic.png|thumb|The master clock (X1) is in region A4 of the [[jwdonal schematic]]]] | ||
=== See Also === | |||
* [[APU oscillator]] | |||
* [[CIC Clock]] | |||
=== Reference === | |||
* http://problemkaputt.de/fullsnes.htm#snestimingoscillators | * http://problemkaputt.de/fullsnes.htm#snestimingoscillators | ||
[[Category:SNES Hardware]] | [[Category:SNES Hardware]] | ||
Revision as of 02:55, 11 July 2023
The Master Clock is 21.48 MHz on NTSC and 21.28 MHz on PAL.
The master clock (X1) is in region A4 of the jwdonal schematic