CMP (SPC700)

Basic Info
Addressing Mode	Opcode	Length	Speed
Immediate	68	2 bytes	2 cycles
Implied Indirect (type 1)	66	1 bytes	3 cycles
Direct Page	64	2 bytes	3 cycles
Direct Page Indexed by X	74	2 bytes	4 cycles
Absolute	65	3 bytes	4 cycles
Absolute Indexed by X	75	3 bytes	5 cycles
Absolute Indexed by Y	76	3 bytes	5 cycles
Direct Page Indexed Indirect by X	67	2 byte	6 cycles
Direct Page Indirect Indexed by Y	77	2 bytes	6 cycles
Implied Indirect (type 1)	79	1 bytes	5 cycles
Direct Page	69	3 bytes	6 cycles
Direct Page Immediate	78	3 bytes	5 cycles
Immediate	C8	2 bytes	2 cycles
Direct Page	3E	2 bytes	3 cycles
Absolute	1E	3 bytes	4 cycles
Immediate	AD	2 bytes	2 cycles
Direct Page	7E	2 bytes	3 cycles
Absolute	5E	3 bytes	4 cycles

Flags Affected
N	V	P	B	H	I	Z	C
	.	.	.	.	.

CMP is an SPC700 instruction that compares two operands. The right operand is subtracted from the left operand, but the difference is not stored anywhere - the side effect is the N, Z, and C flags being modified.

The operands are stored in the instruction stream in the opposite order they appear in the assembler source. In the assembler source, the operand on the right is the source and the operand on the left is the destination.

See Also

• CMPW
• CMP

External Links

• Official Super Nintendo development manual on CMP: Table C-7 in Appendix C-5 of Book I