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OR (SPC700): Difference between revisions
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=== External Links === | === External Links === | ||
* Official Super Nintendo development manual on OR: [https://archive.org/details/SNESDevManual/book1/page/n231 Appendix C-6 of Book I] | * Official Super Nintendo development manual on OR: Table C-8 in [https://archive.org/details/SNESDevManual/book1/page/n231 Appendix C-6 of Book I] | ||
[[Category:ASM]] | [[Category:ASM]] | ||
Revision as of 09:20, 20 November 2023
| Basic Info | |||||||
|---|---|---|---|---|---|---|---|
| Addressing Mode | Opcode | Length | Speed | ||||
| Immediate | 08 | 2 bytes | 2 cycles | ||||
| Implied (type 1) | 06 | 1 byte | 3 cycles | ||||
| Direct Page | 04 | 2 bytes | 3 cycles | ||||
| Direct Page Indexed by X | 14 | 2 bytes | 4 cycles | ||||
| Absolute | 05 | 3 bytes | 4 cycles | ||||
| Absolute Indexed by X | 15 | 3 bytes | 5 cycles | ||||
| Absolute Indexed by Y | 16 | 3 bytes | 5 cycles | ||||
| Direct Page Indexed by X | 07 | 2 bytes | 6 cycles | ||||
| Direct Page Indirect Indexed by Y | 17 | 2 bytes | 6 cycles | ||||
| Implied Indirect (type 1) | 19 | 1 bytes | 5 cycles | ||||
| Direct Page | 09 | 3 bytes | 6 cycles | ||||
| Direct Page Immediate | 18 | 3 bytes | 5 cycles | ||||
| Flags Affected | |||||||
|---|---|---|---|---|---|---|---|
| N | V | P | B | H | I | Z | C |
| . | . | . | . | . | . | ||
OR is an SPC700 instruction that performs a logical or.
The operands are stored in the instruction stream in the opposite order they appear in the assembler source. In the assembler source, the operand on the right is the source and the operand on the left is the destination.
See Also
External Links
- Official Super Nintendo development manual on OR: Table C-8 in Appendix C-6 of Book I